.H 1 "PROCESSOR DEPENDENT HARDWARE (PDH) BOARD"
.ad b
.P
The PDH board contains the processor dependent hardware (real time clock,
stable store, non-volatile memory, front panel LED's, and the processor 
dependent code ROMS) and the IO adapters for the internal and expander CIO
busses.  This chapter gives an overview of the board from a software point
of view.  For more detailed information on the hardware, see the PDH board
Theory of Operation (Dwg No. A-TOPGN-66516-9).
.H 2 "Differences from the Firefox System Board"
.ad b 
.P
As an introduction, this section lists the differences between the 
Firefox system board and the
Top Gun PDH board.
.SP
.DL 5 1
.LI
No floating point math chips.
.LI
Additional CIO channel adapter chip and
circuitry required to interface to an expander.
.LI
Additional 8Kx8 static RAM chip to be used as 
non-volatile memory.  
.LI
Different battery back-up circuit for the real-time clock.
It includes the +5VS supply so that the clock is backed up along with the
memory when a battery back-up box is present.  (The Firefox system board
only uses the front panel batteries for RTC back-up.)
.LI
10 MHz Mid_Bus support.
.LE
.H 2 "Address Space"
.ad b
.P
The PDH address space is decoded by the 
Top Gun SIU.  All accesses to the PDH
are one byte at a time.  Data is returned on bits 0 - 7.  The other 24 bits
are undefined.  The SIU will do word transactions to the PDC (Processor 
Dependent Code) ROM.  The
PDH sees a word transaction as 4 separate transactions.
.P
The PDC is normally accessed in the 1F00_0000 to 1F03_FFFF address space.  It
is also mapped in to the F000_0000 to F003_FFFF address space but not all
bytes can be accessed.  The other PDH hardware is normally accessed in the
F004_0000 to F007_FFFF address space.  It is also mapped to the 1F04_0000 to
1F07_FFFF address space but writes are not allowed there.
.H 3 "PDC ROM"
.ad b
.P

  1F00_0000 to 1F03_FFFF

There is a jumper on the board to determine if the ROM size is 64K bytes
or 128K bytes.  The board will support 2 128K byte ROM's or 3 64K byte
ROM's.  The last 64K bytes of PDC ROM address space is undefined when
64K byte ROM's are used.
The ROM's are also mapped from F000_0000 to
F003_FFFF, but can only be accessed one byte at a time in this area and
only every fourth byte can be accessed.
.H 3 "Stable Store"
.ad b
.P

  F004_0000 to F004_FFFF

The stable store is 8K bytes.  Only one byte can be accessed with every
4 bytes of address space.  The stable store address space is 16K bytes.
It is aliased through the address space.  After writing to stable store
it cannot be accessed for 20 msec.  There is a bit in the status register
indicating when it cannot be accessed.
.H 3 "Non-volatile Memory"
.ad b
.P

  F005_0000 to F005_FFFF

The non-volatile memory is 8K bytes.  Like the stable store, only one byte
can be accessed with every 4 bytes of address space.  The non-volatile memory
address space is 16K bytes.  It is aliased through the address space.
.P
When used, the non-volatile memory maintains useful system configuration 
parameters during power outages.  Loss of this memory may complicate the boot
procedure, but does not require factory intervention to restore processing
capabilities.  For more details, see the IO Initialization ACD. (Note:  At
this time, Top Gun does not use the non_volatile memory.)
.H 3 "RTC/Status"
.ad b
.P

  F006_0000 to F006_FFFF

Like the stable store and non-volatile memory,
only every fourth byte can be accessed.  The RTC is
accessed only 4 bits at a time.  These are bits 4 to 7.  Bits 0 to 3 are
status bits with the following definitions.
All reads from this address space will return this information.  Writes will
have no effect on the status bits.

.DL
.LI
bit 0 - Stable store busy  - If this bit is a one, the stable store is doing
a write.  The EEPROM takes as long as 20 msec to complete a write and cannot
be accessed until the write is completed.
.LI
bit 1 - POW_FAIL  - This is the compliment of the MID_BUS POW_FAIL_L signal.
.LI
bit 2 - CNT_ENABLE - This signal goes to the key switch and is used to enable
remote diagnostics.
.LI
bit 3 - SEC_FAIL  - This is the compliment of the MID_BUS SEC_FAIL_L signal.
.LE

.H 4 "RTC"
.ad b
.P
The 16 nibbles of the RTC chip (MM58274) are aliased through the address space.
The 16 nibbles are briefly described below.  For more information see the
MM58274 data sheet.

.DL
.LI
F006_0000 - Control register - This register contains the data change flag and
the stop/start bit which are used in reading and writing the clock.
.LI
F006_0004 - Tenths of seconds (Read only)
.LI
F006_0008 - Units seconds
.LI
F006_000C - Tens seconds
.LI
F006_0010 - Units minutes
.LI
F006_0014 - Tens minutes
.LI
F006_0018 - Units hours
.LI
F006_001C - Tens hours
.LI
F006_0020 - Units days
.LI
F006_0024 - Tens days
.LI
F006_0028 - Units months
.LI
F006_002C - Tens months
.LI
F006_0030 - Units years
.LI
F006_0034 - Tens years
.LI
F006_0038 - Day of week
.LI
F006_003C - Clock setting - Used for setting leap year and 12 or 24 hour mode.
.LE

.H 3 "LED Latch and FPCLOCK/DATA"
.ad b
.P

  F007_0000 to F007_FFFF

This register is aliased through all the addresses in this space.  Bits 0
through 4 are the five LEDS.  These are turned on by writing a zero to the bit.
Bit 5 is the PROCFAULT LED.  Bit 7 is FPDATA and bit 6 is FPCLOCK.
.H 4 "FPCLOCK and FPDATA"
.ad b
.P
There are two ways of using the FPCLOCK and FPDATA lines.  The first is to
meet the spec of the AP card.  The second is slower to allow it to be used
in environmental testing.  Using the FPCLOCK/DATA lines will cause the LED's
to be written.  The software must know what is on the LED's so that the same
data can be written out.  The LED register cannot be read.
.H 5 "AP Card Use"
.ad b
.P
The following procedure should be used to write to the AP card:
.AL
.LI
Write the first data bit to FPDATA.
.LI
Enable the FPCLOCK by writing a one to the FPCLOCK bit.  This will enable the
FPCLOCK and also cause the first data bit to be clocked into the AP card.
.LI
Write the remaining data bits.  All writes to the LED and FPCLOCK/DATA register
will cause a bit to be clocked into the AP card.
.LI
When all the bits have been written, disable the FPCLOCK by writing a zero to
FPCLOCK.
.LE

.H 5 "Environmental Test Use"
.ad b
.P
It was desired to monitor the FPCLOCK and FPDATA lines with a controller during
environmental test.  This required that the FPCLOCK line change slow enough so
that software could detect when it was pulsing.  The following procedure should
be used when the lines are used in this way:

.AL
.LI
Write the first data bit to FPDATA.
.LI
Enable FPCLOCK by writing a one to the FPCLOCK bit.
.LI
Wait long enough to insure the monotor program can see that the FPCLOCK line
has changed.
.LI
Disable the FPCLOCK by writing a zero to the FPCLOCK bit.
.LI
Wait long enough to insure the monotor program can see that the FPCLOCK line
has changed.
.LI
Repeat the above steps until all the bits have been sent.
.LE

.H 2 "Clock Calibration"
.ad b
.P
The clocks will be calibrated to within .1 ppm (An error
of 1 ppm would cause the clock to gain or loose 2.5 seconds/month.) at the
factory.  The clocks are calibrated by use of software and the EEPROM
on the PDH board.  This section explains how the calibration constants are
kept in the EEPROM and gives an example of how the software can use these
to insure accurate time.  It will be possible to adjust the
calibration constants with software (in the field) but this should not be
necessary.
.P
The system clock is used to keep time while the machine is powered up and the
TOD clock keeps time when the machine is powered down.  The TOD clock is read at
power up and set to match the system clock when the machine is powered down.
.H 3 "System Clock"
.ad b
.P
The CR16 interval timer will count at about 15.0 MHz (assuming that Top Gun
has a 30 MHz clock).  PDC_TOD will return
a double-precision floating point value equal to the interval timer
frequency in mega-cycles/second.  This value will be used to calculate
a constant that will be added to the CR16 comparison register each time
there is a timer interrupt.  The constant is calculated by dividing
the interval timer frequency by the desired interrupt frequency (in MHz).
.P
The last value written to CR16 needs to be saved in memory (as opposed to
just reading CR16 to get the value) to insure
that the uncertainty in the interrupt response time does not cause the clock
to drift.  The fractional part of the result of adding the count constant
to CR16 should also be saved to be added into the next value.  This will reduce
the drift due to rounding errors.

.DL
.LI
Example:  If count frequency was 15.005 MHz and the interrupt frequency
was 10 KHz the count constant would be 1500.5.  If the fractional part was
not saved the drift would be .5/1500 (333 ppm) which would be 14 minutes per
month.
.LE

.H 4 "Keeping Accurate Time"
.ad b
.P
This section discusses an algorithm for keeping accurate time with the CR16
interval timer.  There are three procedures involved.  Some constants have
to be initialized, an interval timer comparison register has to be initialized
and the interval timer comparison register has to be updated.
.P
There are four 32 bit words of memory that need to be initialized and updated:

.VL 20 5 1
.LI count
This is the number of interval timer counts between
interrupts.
.LI count_fraction
This represents the fraction number of counts
to make it come out exact.
.LI count_save
This is used to save the last value loaded into
CR16.
.LI fraction_save
This is the remainder from the last time the
value to load into CR16 was calculated.
.LE

It is assumed that the following two double-precision floating point numbers
will be passed to the routine that initializes the constants:

.VL 20 5 1
.LI clock_freq
The frequency at which CR16 is counted.
.LI interrupt_freq
The frequency at which CR16 is to interrupt.
.LE

The following algorithm initializes count and count_fraction.  This is only
executed at power up.

.DS
.ft LP
.ps 12
	begin
{Making the most significant bit of temp1 and temp2 0 simplifies 
the algorithm}
	temp1:=(the 31 most significant bits of the fraction part of
		clock_freq)/2
	temp2:=(the 31 most significant bits of the fraction part of
		interrupt_freq)/2
	temp3:= 2 exp (mantissa of clock_freq - mantissa of
                interrupt_freq)
.ft R
.ps 10
.DE
.DS
.ft LP
.ps 12
{calculate count by dividing the clock frequency by the interrupt rate}
	count := 0
	while temp3 > 0 do
		begin
		if temp2 < temp1  do
			begin
			count := count+temp3
			temp1 := temp1-temp2
			end
		temp3 := temp3/2
		temp1 := temp1*2
		end
.ft R
.ps 10
.DE
.DS
.ft LP
.ps 12
{calculate the fractional part by dividing the remainder}
	count_fraction:=0
	temp3 := 2 exp 31
	while temp3 > 0 do
		begin
		if temp2 < temp1  do
			begin
			count_faction:= count_faction+temp3
			temp1 := temp1-temp2
			end
		temp1 := temp1*2
		temp3 := temp3/2
		end
	end
.ft R 
.ps 10
.DE

The following initializes the CR16 counter, count_save, and fraction_save.

.DS
.ft LP
.ps 12
	begin
	count_save := CR16+count
	CR16 := count_save
	fraction_save := count_fraction
	end
.ft R
.ps 10
.DE

The following updates CR16, count_save, and fraction_save.

.DS
.ft LP
.ps 12
	begin
	fraction_save := fraction_save+count_fraction
	if overflow then count_save := count_save+1
	count_save := count_save+count
	CR16 := count_save
	end
.ft R
.ps 10
.DE

.H 3 "TOD Clock"
.ad b
.P
The TOD clock is implemented with a National MM58274.  The data sheet should
be consulted for details on how to set and read the time.  The TOD clock
keeps time in years, months, days, hours, minutes, and seconds.  The PDC
must translate this into seconds when it reads the time and back to
the TOD format from seconds when it sets the time.  A calibration
constant will be saved in the EEPROM.  This will allow an inexpensive,
low accuracy crystal to be used with the clock chip without the problems
of a trimmer capacitor and still enable it to keep very accurate time.
.H 4 "Setting The TOD Clock"
.ad b
.P
The following things are done to set the TOD clock:
.AL
.LI
The time is received by the PDC as seconds since 00:00:00, January 1, 1970.
(The microseconds word is ignored.)
.LI
This number is multiplied by the inverse of the calibration constant.  The
inverse of the calibration constant will be stored along with the calibration
constant so that the PDC does not have to do a divide.
.LI
The seconds are converted to the TOD clock chip format.
.LI
The time is written to the TOD clock chip.
.LE

.H 4 "Reading the TOD Clock"
.ad b
.P
The following steps are taken to read the TOD clock:
.AL
.LI
The TOD clock is read.
.LI
The TOD clock chip format is converted to seconds since 00:00:00, January 1,
1970.
.LI
This value is multiplied by the calibration constant.
.LI
The microseconds word is set to zero.
.LE

If it takes a long time to read and write the clock it may be necessary
to add an offset when the clock is read and written to keep the clock
from drifting.
.H 2 "Stable Store Allocation"
.ad b
.P
This section describes how the stable store is used.  There is information
in stable store that is required to be valid and is changed by the operating
system at times.  The stable store is implemented with an EEPROM.
.P
The stable store takes a long time to write and so provisions have been made
to insure that bad data is not written in the event of a power fail.
The stable store is divided into 4 areas (512 bytes each).  The Top Gun
PDC always writes to stable store in double word blocks.
.H 3 "The First Two Areas"
.ad b
.P
The first two areas are duplicates of each other.  They contain the information
needed by the operating system.  For details on what this information, see
the IO Initialization ACD.  This information is kept in two areas to insure
that a valid copy is available if power goes down while the information is being
changed.  A separate check sum is kept for each area.
.H 3 "The Third Area"
.ad b
.P
This area is used for PDH information.  At this time the only thing kept in
this area is the calibration constants for the real time clock and the system
clock.
.H 4 "System Clock Frequency"
.ad b
.P
This is a double-precision floating point number, that gives the exact
frequency of the CR16 counter (about 15.0 MHz).  This number is returned to the operating
system and is intended to be used to keep real time during power up.  It
is located in the first 8 bytes of the PDH area (MSB first)
.H 4 "Real Time Clock Calibration Constant"
.ad b
.P
The second 8 bytes of the PDH area contain the calibration constants for the
real time clock.  The first 4 bytes contain the constant that the real time
is multiplied by when it is read (MSB first).
If the time is exact, the constant will
be 80000000 Hex.  If it is slow it will be larger, and if it is fast it will
be lower.  When the time is read it is multiplied by the calibration
constant and then multipled by two.  The most significant word of this
operation gives the corrected time.
.P
The next 4 bytes contain the constant that the time is multipled by before
it is written to the real time clock.  This number is the effective inverse of
the first number.  It is provided so that the PDC does not have to do a divide.
.H 4 "Number of Tic's per 10 msec."
.ad b
.P
Bytes 28 through 31 (hex address) contain the number of tic's of the CR16 counter in 10 msec
(LSB first).
The CR16 counter counts at one half the rate of the system clock (about 15.0
MHz).  This number is not supposed to be used when accuracy is needed but it
will be made exact on Top Gun anyway. (UNIX uses it to keep real time.)
.H 3 "The Fourth Area"
.ad b
.P
This contains the check sums for the other three areas.  It is divided into
three areas on double word boundaries. Each area consist of 168 double word
entries.  The double word is divided into two words.  The first word contains
the check some for the corresponding area.  The second word contains a count.
Every time that a double word is written to stable store the check sum is
recalculated and written and the count is incremented.  The EEPROM can only
be written to 10000 times and so the count is needed to insure that the check
sum is not written to more than 10000 times.  When the count reaches 9500 the
next check sum location is used.  The check sum area is treated special because
each time any double word location is written, the check sum is updated and
so this area will be written much more often than other areas.
.H 2 "Non-volatile Memory Allocation"
.ad b
.P
At this time, the non-volatile memory is not used.  In the IO Initialization
ACD, use for the non-volatile memory is architected and will be implemented
on Top Gun in the future.
.H 2 "Channel Adapter Chips"
.ad b
.P
The PDH board also contains one or two CIO channel adapter chips.  The CIO channels provide
the interface between the midbus and the CIO bus.  The CIO channel on the one channel PDH board is
for the internal CIO bus.  The two channel PDH board includes an additional channel for interface
to an expander CIO bus.  It is this second chip that allows an expander to be used with Top Gun.
From a software point of view, the internal channel is at midbus
address 4 (slot 1, module 0) and the external channel is at midbus address
36 (slot 9, module 0).  
The second channel was hardwired to slot 9, module 0 rather than slot 1, module
1 (the more logical choice) for diagnostic reasons.  When an I/O module fails,
the front panel displays which slot, NOT which module.  Therefore, if both
channels were in slot 1, one could not tell which channel failed if an error
is flagged.
The IODC for both of the channels is the same and
is found in one of the PDC ROMs.

.P
Top Gun meets the HP Corporate Class B2 Environmental specifications.  It
complies with the same safety, EMI, and acoustic regulations that Firefox
does.  The following sections list these specifications.
An asterisk (*) by a title signifies that
the area was not affected by the Top Gun board replacement and re-certification
was not necessary.
.H 2 "Safety Compliances"
.ad b
.P
Top Gun complies with the following safety regulations:
.P
.TB "Safety Compliances"
.SP
.ad l
.TS
box center tab(:);
cb|cb|cb|cb
lfR |cfR |cfR |lfR .
Regulatory Specification:T{
Verify Compliance
T}:T{
Obtain Certification
T}:T{
Type~of Certification
T}
=
UL 478, 5th edition *:Yes:Yes:UL listed
CSA 22.2, No. 154 *:Yes:Yes:CSA certified
IEC 380, 2nd Edition *:Yes:No
IEC 435, 2nd Edition *:Yes:No
.TE
.P
.H 2 "EMI Compliances"
.ad b
.P
A minimum Top Gun system complies with the following EMC regulations:
.P
.TB "EMI Compliances"
.SP
.ad l
.TS
box center tab(:);
cb|cb|cb|cb
lfR |cfR |cfR |lfR .
Regulatory Specification:T{
Verify Compliance
T}:T{
Obtain Certification
T}:T{
Type~of Certification
T}
=
FCC Part 15J Class A (see Note):Yes:No
FTZ 1046/1984 w/ 2db margin:Yes:No
South African Bureau of Standards:Yes:Yes:SABS certified
VCCI (CISPR 22 class A):Yes:Yes:VCCI registered
.TE
.ad b
\fINote:\fR  FCC Compliance is verified by testing to the
more stringent FTZ 1046/1984 levels.
.P
.H 2 "Miscellaneous Compliances"
.ad b
.P
Top Gun also complies with the following standards:
.P
.TB "Miscellaneous Compliances"
.SP
.ad l
.TS
box center tab(:);
cb|cb|cb|cbw(1.5i)
lb|lfR |cfR |lfR .
Category:Standard:T{
Verify Compliance
T}:Complies in
=
Ergonomics:ZH1/618:Yes
_
Acoustics:T{
HP internal, < 50 dbA
T}:Yes
_
T{
Datacom Licensing *
(for AP and 6-port MUX)
T}::Yes:T{
Australia, Belgium, Finland, Germany, Sweden,
United Kingdom (see note).
T}
.TE
.P
.ad b
\fINote:\fR  These are the only countries requiring datacom
licenses for these products.
.bp
.P
.H 2 "Environmental Test Specifications"
.ad b
.P
The following table lists the environmental test specifications used
to verify Class B2 specifications.  An asterisk (*) denotes that
the area is minimally affected by the Top Gun board replacement and that the
tests are pre-qualified (the tests are performed only once during the
Lab Prototype phase).
.P
.ad l
.TB "Environmental Test Specifications"
.SP
.ad l
.TS
center box tab(:);
cb p+2 |cb p+2 
lfR |lfR .
Parameter:Test Specification
=
\fBTEMPERATURE\fR
~~Operating:0 to 55 deg. C
~~Non-operating--storage:-40 to 75 deg. C
~~Rate of change:20 deg. C / hr.
_
\fBHUMIDITY\fR
~~Operating - non-condensing:5 to 95% RH at 40 deg. C (24 hours)
~~Operating - condensing:T{
0 C, then
50% Humidity at 25 C
T}
~~Storage - non-operating:95% RH at 40 deg. C
~~Condensation recovery:T{
Within 15 minutes;
50% RH at 25 C,
then 95% RH at 40 C
T}
_
\fBALTITUDE~*\fR
~~Operating:T{
15 Kft, derate temperature
at -1.1 deg. C / Kft above 7.5 Kft
T}
~~Non-operating:50 Kft
_
\fBVIBRATION\fR
~~Operational (random)
~~~~5-350 Hz:0.0001 g^2/Hz 
~~~~350-500 Hz:-6 db/octave
~~~~500 Hz:0.00005 g^2/Hz
:
~~Non-operational, survival (sine):0.5g peak, 5 to 500 Hz
:
~~Non-operational, survival (random):2.09 g RMS
~~~~10-100 Hz:0.015 g^2/Hz
~~~~100-137 Hz:-6 db/octave
~~~~137-350 Hz:0.0008 g^2/Hz
~~~~350-500 Hz:-6 db/octave
~~~~500 Hz:0.0039 g^2/Hz
:
~~Package (swept sine):0.5 g p-p, 5-200 Hz
:
~~Package (random):1.47 g RMS
~~~~5-100 Hz:0.15 g^2/Hz
~~~~100-200 Hz:-6 db/octave
~~~~200 Hz:0.0038 g^2/Hz
.TE
.P
\fI(Continued next page)\fR
.bp
.TS
center box tab(:);
cb p+2 |cb p+2 
lfR |lfR .
Parameter:Specification
=
\fBSHOCK\fR
T{
~~End use handling, Unpackaged
T}:T{
60 Inch/Sec, approx 120 G <3.0 msec
half sine waveform
T}
T{
~~Transportation Survival
T}:T{
238 ips velocity change, trapezoidal waveform
T}
T{
~~Packaged Impact Test
T}:T{
24" freefall,
10 impacts (6 faces, 4 bottom corners)
T}
_
\fBESD\fR
~~No effect:0 to 15 KV
~~No hardware failures:15 KV to 25 KV
_
\fBELECTRIC FIELD IMMUNITY~*\fR
~~Radiated
~~~~14 kHz to 1 GHz:5 V/meter
~~Conducted
~~~~50 kHz to 400 MHz:1 V RMS
_
\fBMAGNETIC EMISSIONS~*\fR
~~Non-operating:< 5.25 mgauss at 4.6 m
~~Operating:< 1 gauss p-p
~~Field Immunity:T{
4 gauss p-p, 48 Hz to 198 Hz
T}
_
\fBAC LINE VOLTAGE~*\fR
T{
~~AC line input nominal
T}:100/120/240 VAC
:9.5/8.0/5.3 Amps
~~Variations:T{
Non-continuous variations,
90-132 VAC, 180 to 264 VAC
T}
~~Line Frequency:50-60 Hz
~~~~Variations:48-66 Hz
T{
~~Power Fail Recovery (Standby)
T}:30 minutes
T{
~~Power Fail (Carry through)
T}:1 cycle min.
~~Power line transients:T{
1 kV pulse, 1 nsec risetime, 800 nsec duration;
Peak of twice nominal line voltage, 500 ns risetime,
10 usec duration
T}
.TE
.R
.H 1 "RELIABILITY AND SERVICEABILITY" 
.ad b
.P
The reliability and serviceability goals of Top Gun are the same as
Firefox.  To meet this goal, the Top Gun processor and PDH boards must
be equivalent in reliability and serviceability to the Firefox processor
and system boards.
.H 2 "Reliability
.ad b
.P
The reliability goals set by the QA department state that the failure rate
for a new product should be one percent per year for each $1000.00 of the 
target list price.  A failure is considered to be any failure which requires
a service call.
.P
For a system, the failure rate is to be allocated among the various 
components in proportion to their list price.
In order to meet the QA department's goal, Top Gun must match or improve on the
failure rates for the Firefox processor and system boards using %/K$ factory
cost.  
Note that this assumes the multiplier used for Top Gun will be at least
that used for Firefox, which should be a conservative assumption.
The Firefox failure rates to meet are the 
following:
.P
.VL 30 10 1
.LI "Processor board:"
2.04%/$1000 factory cost
.LI "System board:"
2.64%/$1000 factory cost
.LE
.P
The Top Gun failure rate will be verified in two ways.  First, the QA 
department will use a program called MLDB to calculate the failure rate
for each board.  The program uses the parts list and the known field failure
rates for the parts to calculate the failure rate.  Second,
the observed failure rate during strife
testing is multiplied by a factor based on 
experience from past projects.  The QA
department uses a multiplier of five to estimate the field failure rate.   (The failure rate measured in strife
testing has been five times greater than the failure rate measured in the 
field.)
.H 2 "Serviceability"
.ad b 
.P 
The serviceability goal for Top Gun is to provide, at the minimum, the
service features of Firefox.
.P
The system contains the same number of FRU's as Firefox, but
the processor board contains a larger percentage of the system's
components.
.H 3 "Diagnostics"
.ad b
.P
Self-test and ISL to test the system prior to OS boot 
are nearly identical to that in Firefox.
Diagnostics are equivalent to that used in Firefox.
However, moving the math chips to the processor board enhances
FRU identification beyond that in Firefox.  (In Firefox,
many math system failures cannot be diagnosed to the board,
since the interface extends across both boards.)
.H 4 "Error Reporting"
.ad b
.P
As in Firefox all pre-Console errors are logged on the system status
LED's on the SPU.  All other errors are reported to the system
console.
.H 4 "Remote Diagnosis"
.ad b
.P
Remote diagnostic capabilities using
the CIO-based AP card are still supported.
.H 3 "MTTR"
.ad b
.P
MTTR for Top Gun is similar to Firefox.
Due to the increased amount of logic on the processor board,
diagnosis time should be reduced slightly over Firefox.
.H 3 "Annual Repair Costs"
.ad b
.P
The annual repair cost (ARC) of the Firefox processor and
system board is currently estimated to be 1.6% of list price.
Since Top Gun is slated to have the same %/K$ failure rate 
based on factory cost, and assuming the multiplier used
for Top Gun will be the same as Firefox, ARC should be 1.6% of
list price.
