
.DF

                                                      1/4/88
                                                 Rob Horning
.DE


This is a summary of the clock specs for PCX.  There are many things that
need to be specified, but only the two most critical are listed below.

.DF
                                      min   max
        CPU clock to ECLiPS buffer    .25    .5
        ECLiPS buffer                 .6     .8
        ECLiPS buffer to CMUX clock  1.9    5.03
        PC board TD variation        -.05    .05
                                    _____  ______
                                     2.7    6.38
.DE

The above numbers are the actual numbers measured on the simulations.
The simulations were done in two parts.  The first was from the clock inside
the CPU to the ECL driver and the second was from the ECL driver to the clock
inside the CMUX.  The input to the ECL driver was modeled as a capacitor.
The output was modeled with two voltage sources in series with a resistor
and a diode.  One source pulls the line high and the other keeps the line
from going all the way to zero.  Doing this gave a model that acted like the
real part.  The time delay variation for the PC board was put into the
simulations because it is assumed to be independent of the other variables.
The variables that were included were temperature, voltage, models, PC board
impedance, PGA models, rise time, and voltage swing.

When the simulations were started there was a lot of concern about being able
to provide good ECL levels to the ECL driver.  It was discovered the the ECL
buffer does not require ECL levels.  It is a true differential buffer.  We
are working on getting a spec that takes advantage of this.  The simulations
assumed that we would regulate the reference voltage for the CMOS clock driver.
We will put a regulator on the first PC board, but it is likely that we will
be able to replace it with a resistor.

In some of the cases a large glitch is seen at the output of the ECLiPS driver.
This does not show up at the CMUX.  It is caused by the capacitive loading of
the CMUX.  This should not cause a problem, but it should be mentioned to
Motorola to make sure that it will not cause a problem with the ECLiPS part.

Simulation conditions:
.DL
.LI
Timing starts when the CPU clock crosses VDD/2.  For fast case it will
start when the later of the two clocks crosses and for slow case it will start
when the earlier of the two clocks crosses.
.LI
The timing ends when the CMUX clock crosses VDD/2.  For fast case it will
end when the earlier of the two clocks crosses and for slow case it will
end when the later of the two clocks crosses.
.LI
ECLiPS Clock Buffer Specs:
.DL
.LI
Input capacitance - 1 pF to 2 pF
.LI
Rise Time - 300 pS to 700 pS
.LI
Voltage swing - .4 to 1 volt and .1 to 1.3 volts
.LI
Delay - 0.6 to 0.8 ns
.LI
Timing for the part was measured from input crossover to output crossover.
.LE
.LI
PC Board - Z0 = 30 to 50 Ohms, TD = 1.05 to 1.15 ns.
.LI
For most simulations nominal PGA was used.  Slow PGA was used for slow
cases.  It made about a 50 pS difference.
.LI
Fast case used 60 pF on CK1 and CK2 in the CMUX.  Slow case used the clock
distribution model (attached).
.LI
Clocks in the CMUX are loaded equally.
.LI
The CPU clocks are symmetrical.
.LE

The model used for the CMOS driver to ECL receiver is on hpesrjh:

/users/rob/mydesigns/ECLNS1

The SLE is the slow case and FAE is the fast case.


The model used for the slow case ECL driver to the CMUX receiver is on hpesrjh:

/users/rob/mydesigns/CKRS1

The SSS is the slowest case.


The model used for the fast case ECL driver to the CMUX receiver is on hpesrjh:

/users/rob/mydesigns/CKR3

The FSS case is the slowest case.

The above two simulations reference parts on hpesprb and hpesrmc under
/users/prb(rmc)/mydesigns.

