
This is the latest estimates of the PC board models.  It will be updated as the
PC board is designed.  These models supersede all previouse modles that were
given out.

If you need models for busses that are not included here let me know and I will
try to add them.  Some of the models are conservative and with some work they
can be improved.  Let me know of any signals that you would like to see
improved.

DCD Bus -

The DCD bus connects the data CMUX chips to the CPU and the Coprocessor.  It
is assumed that the DCD can go on any layer.  The impedance can be between
33 and 86 Ohms.  For traces that have more than two pins connected it is
possible for one trase to be 36 Ohms and the other 86 Ohms.

The 32 traces that connect only from the CMUX chips to the coprocessor will be
from .2 to 1.3ns long.

The traces that connect to both the CPU and FPC will be from .2 to .4 ns
long for the shorter trace and .3 to .5 ns long for the longer trace.
Half the traces will have the CPU in th emiddle and the FPC and CMUX on the
ends and half will have the FPC in the middle and the CPU and CMUX on the ends.

Data Cache Tag Lines -

 	Z0 - 33 to 86 Ohms
        TD - .3 to .6 ns and .5 to 1.0 ns

Each data tag line goes to both CMUX chips.  One of the CMUX chips is closer
to the RAM's than the other.

Data Cache Data Lines -

	Z0 - 33 to 86 Ohms
        TD - .3 to 1.0 ns

The time delay forthe data lines could be matched to make the range .8 to
1.0 ns.

Data Cache Address -

Data RPN -

PMI Bus -

NIO -

ICD Bus -

Instruction Cache Tag Lines -

Instruction Cache Data Lines -

Instruction Cache Address -

Instruction RPN -

Coprocessor -

Floating Point Chips -

