
.DF
                                                     3/1/88
                                                     Rob Horning
.DE

This a summary of the testing that I did with the Hitachi 15 ns SRAM and
the Hitachi SRAM SPICE model.


Conclusions:
.AL
.LI
The preliminary specs that I distributed for low level output, high level
output, and rise time are still valid.
.LI
The budget for data cache data delay can be met. (1.5 ns).  This assumes that
the data lines are less than 3 inches long.
.LI
The budget for the data cache tag line delay will not be met.  We will need
2.5 to 3 ns.
.LI
It dose not look likely that I will be able to come up with a generic spec
for the output drivers.  (More on this later.)
.LE


What Was Done:

I built a circuit that would write 2 four bit words into a 16K x 4 SRAM.  What
was written was determined by a set of switches.  The words were different by
only on address bit.  After writing the words into the SRAM,
the SRAM was put into read mode and the address line toggled continuously.
While the outputs were toggling I would disconnect the buffers used to
write data to the SRAM and add a load circuit.

The loads that I looked at are listed below:

.AL
.LI
No load.
.LI
Hitachi test load (30 pF, 470 Ohms to +5, 260 Ohms to ground)
.LI
Capacitive load. (30 pF)
.LI
Tag line. (50 Ohm 1 ns coax to 15 pF plus 50 Ohm .5 ns coax to 15 pF)
.LI
Slow data line. (37.5 Ohm .6 ns coax to 12 Ohms)
.LI
Fast data line. (75 Ohm .6 ns coax to 2 Ohms)
.LE

I also used the Hitachi spice model to compare the test results to what the
model predicts.  The spice simulations helped determine why the output driver
acts like it does, because I could look at some internal nodes.  It also let
me test the sensitivity of some some parameters that could not be changed on
the test circuit.  (Driver size, package inductance, etc)


Output High Level:

One of the most interesting things that I observed was that the output high
level was very load dependent.  This was expected for a resistive load, but
it varied even more for non-resistive loads.  Capacitive loads and combinations
of transmission lines and capacitors, had a higher output level than having
no load on the output.  There are at least two things that could be causing
this.
.AL
.LI
The output rings up and stays up.  When the output driver drives the package
inductance into a capacitive load the ringing causes the level to go higher.
With no resistive load the level stays high until the SRAM drives it low.
.LI
The pad Vdd on the SRAM rings and when it goes higher than Vdd it causes the
output driver to drive higher.  Again the output level remains at the high
voltage because there is no resistive load.
.LE

Both reasons seem to have an effect.  One problem is that both of these effects
are very tuned and not only load dependent but also pattern dependent.  The
result is that we are likely to get much higher output levels than the vendors
will be able to spec or than we can count on worse case.  If the SRAM package
was improved the typical output high level would go down.

A good high level can help the receiver detect a low to high transition, but
it will cause high to low transition to be slower because the voltage swing is
greater.  The test circuit and spice simulations both showed the penalty
for an extra volt of high level to be on the order of .5 ns.  (Assuming about
30 pF of capacitive loading.)

As would be expected the slowest case is the low impedance transmission line
with a high capacitance load.  In this case the typical driver sees the load
as a capacitive load for the most part.  The PCX1 data lines will have a worse
case capacitance of about 30 pF.  The PCX1 tag lines have about 60 pF.  The
extra 30 pF causes about 1 to 1.5 ns of additional delay.


Output Driver Turn Off:

The Hitachi models show the output driver turning off before it starts driving.
With no resistive load this effect cannot be seen, however with the test load
it does show up.  With the test circuit on high to low transitions the driver
seemed to turn off about 1 ns before it started to drive low.  This gives the
test load a small head start on the non-resistive loads that I tested
(about .1 ns).  The .1 ns is not a problem, but if the number became larger it
could be a problem.

Example: If the output driver turned off 5 ns after an address transition
and then started driving low at 12 ns, the test circuit would have pulled
the output most of the way to 1.5 volts before the driver turned on.  This
could make a part look faster than it really is.

We will want to spec the timing with a large value pull up resistor to 4 or 5
volts and 30 pF.  It is likely that this would require about a 1 ns to be
added to the access time.


Vendor Specs:

I would like to add the following things to the specs that we give to the
SRAM vendors:

.AL
.LI
The output high level will be 2.9 volts when the there is less than 1 mA of
DC load and VCC is at least 4.75 volts.
.LI
With the standard test load of 480 Ohms to +5 volts, 255 Ohms to ground, and
30 pF to ground, the transition time will not be greater than 5 ns.  This is
the time to go from 2.9 to .4 volts.
.LI
If the test load is changed to 10K Ohms to +5 volts and 30 pF to ground, the
access time will not increase by more than 1 ns.  The purpose of this spec is to
insure that the output driver can drive a larger voltage swing with only a
small access time penalty.  The cycle time for this test needs to be at
least 500 ns to insure that the 10K resistor has time to charge the 30 pF
capacitor.
.LE

The above specs do not have to be 100% tested.  They only need to be
guaranteed.  This can be done by characterization and/or sampling.


Receiver Specs:

We should use the following specs when evaluating timing and receivers for
the CMUX:

.AL
.LI
Output high - 2.5 volts
.LI
Output low - .8 volts.
.LI
Data cache data delay - 1.5 ns.
.LI
Data cache tag delay - 3.0 ns.
.LI
Instruction cache data and tag delay - 2.0 ns
.LI
Rise and fall times for tag lines - 3.5 ns (2.5 to .8 Volts)
.LI
Rise and fall time for data lines - 2.5 ns (2.5 to .8 Volts)
.LE

These specs allow for PC board delay and noise.

For fast case assume transitions between 0 and 4 volts in 1.3 ns.  This should
be driven into 10 Ohms then a 1 ns 35 Ohm transmission line.  The transmission
line is only to give under-shoot, and should not be used to give minimum delay.
The minimum delay is zero.  It is assumed that the CMUX IO will provide
clamping.

For worse case power assume that the output high voltage is 3 volts.  This is
with VCC set to 5.25 volts.  Assume that it takes 10 ns to get up to 3 volts
(from .8 volts).

