
.H 1 "Preliminary Target Specification for a 64K x 4 15 nS SRAM"

This is a second pass target specification for a 64K x 4 15 nS SRAM.
The package is assumed to be a 24 pin, 300 mil SOJ.

Changes from the first pass specification have been noted.  Specifications
have been added for access time penalties for larger loads.  Input capacitance
specifications have been expanded.  The specifications for the input wave forms
have been modified.


.DS
DC OPERATING CONDITIONS
.TS
tab (/) allbox;
lccccc.
Symbol/Parameter/Min/Max/Units/Notes
_
VCC/Supply Voltage/4.75/5.25/V
TEMP/Ambient Temperature/0/70/C
VIH/Input High Level/2.2/VCC+0.5/V/2
VIL/Input Low Level/-0.5/0.8/V/1
.TE

Note 1: VIL = -3.0 Volts for pulse widths less than 10 nS.

Note 2: This specification has been relaxed.
.DE


.DS
DC ELECTRICAL CHARACTERISTICS
.TS
tab (/) box;
l|c|c|c|c|c|c.
Symbol/Parameter/Conditions/Min/Max/Units/Notes
=
ILI/Input Leakage Current/VCC=Max./-/10/uA
_
ILO/Output Leakage Current/VCC=Max./-/10/uA
_
VOL/Output Low Voltage/IOL = 8 mA/-/0.4/V
_
//IOH = -100 uA/2.9/ /V/1
VOH/Output High Voltage/_/_/_/_/_/_
//IOH = -4 mA/2.4/ /V
.TE

Note 1: This parameter is guaranteed but does not have to be 100% tested.
.DE


.DS
POWER
.TS
tab (/) allbox;
l|c|c|c|c|c|c.
Symbol/Parameter/Conditions/Min/Max/Units/Notes
-
ICC1/Supply Power/f=50 MHz/-/115/mA/1,2
ICC2/Supply Power/f=0/-/90/mA/1
.TE
Note 1: Maximum power is measured with the chip enabled, VCC=5.25, and the
           outputs open.

Note 2: This specification has been relaxed.  Power has been increased and the
           frequency has been reduced.
.DE


.DS
AC ELECTRICAL CHARACTERISTICS
.TS
tab (/) allbox;
lccccc
lscccc
lccccc.
Symbol/Parameter/Min/Max/Units/Notes
Read Cycle/ / / / 
_
tRC/Read Cycle Time/15/-/ns
tAA/Address Access Time/-/15/ns
tACS/Chip Select Access Time/-/15/ns
tCLZ/Chip Select to Output in Low Z/3/-/ns/1
tCHZ/Chip Select to Output in High Z/-/8/ns/1
tOH/Output Hold After Add. Change/4/-/ns/1,2
.TE

Note 1: This specification has been relaxed.

Note 2: This is a critical specification.  It is almost as important as address
           access time.
.DE


.DS
AC ELECTRICAL CHARACTERISTICS
.TS
tab (/) allbox;
lccccc
lscccc
lccccc.
Symbol/Parameter/Min/Max/Units/Notes
Write Cycle/ / / / 
_
tWC/Write Cycle Time/15/-/ns/
tCW/Chip Select to End of Write/15/-/ns/
tAW/Address Valid to End of Write/15/-/ns/
tAS/Address Set-up Time/2/-/ns/1
tWP/Write Pulse Width/10/-/ns/3
tWR/Write Recovery Time/2/-/ns/2
tWHZ/Write Enable to Output in High Z/-/8/ns/2
tDW/Data Valid to End of Write/10/-/ns/2
tDH/Data Hold Time/0/-/ns
tOW/Output Active from End of Write/3/-/ns/2,4
.TE

Note 1: This specification has been relaxed.  It is not critical for the
          current designs but it may be for future designs.

Note 2: This specification has been relaxed.

Note 3: This specification has been made tighter.

Note 4: When a write cycle is ended with WE, the data driven by the SRAM (after
           tOW) must be the same data that was just written.  This assumes that
           the address does not change.  This is necessary to prevent a drive
           fight between the SRAM and the controller.

Note 5: Write cycles are started when both CS and WE are asserted (the order
           does not matter) and are ended when CS or WE is de-asserted.  It does
           not matter which signal is de-asserted.
.DE


.DS
CAPACITANCE
.TS
tab (/) allbox;
lccccc.
Symbol/Pins/Min/Max/Units/Notes
_
Cin/Input - 3-9, 19-22/1/3.5/pF
Cin/Input - 1, 2, 10, 11, 13, 23/1.5/4.5/pF/1
Cout/Outputs - 14, 15, 16, 17/0/7/pF/1
.TE

Note 1: This specification has been relaxed.
.DE


Input Signals:

AC electrical specifications are guaranteed with input signals that change
between .8 and 2.4 volts with a rise/fall time of less than or equal to 4 ns.
Both input and outputs are measured from 1.5 volts.  Signal are not required
to change monotonically.

All input signals may have very fast rise and fall times.  Inputs may change
from 0 volts to 5 volts in 0.5ns.

Output Loads:

Specifications are guaranteed with the three output loads shown on the following
page.

Load 2 is used for tOH, tHZ, tLZ, tWZ, and tOW.

All other AC specifications are guaranteed with load 1 except for the access
time penalties listed below.  Penalties are added to all access times when the
given loads are used.

.DS
LOAD ACCESS PENALTIES
.TS
tab (/) allbox;
ccccc.
R1/R2/C/Penalty/Notes
_
480 Ohms/255 Ohms/30 pF/0 nS/1
Open/Open/30 pF/0.5 nS/1
Open/Open/60 pF/1.5 nS/1
Open/1 KOhm/60 pF/1.0 nS/1
.TE

Note 1: R1 is connected between VCC the output.  R2 and C are connected between
           ground and the output.
.DE

