.PH "''''''"

.DF
From: Rob Horning                            Date: 2/12/87

  To: Eric Delano                         Subject: Cache Dump
      Howell Felsenthal
      Dan Halperin
      Bill Jaffe

.DE
This is a summary of how the cache dump to main memory works on PCX1 (for
power fails).  It is important
that the full bandwidth of the NIO be used to insure that the cache can
be flushed in the 30 msec. of hold-up time provided by the power supply.
If any of the assumptions that I have made are wrong please let me know
as soon as possible.

The following assumptions are made on the NIO side:
.AL
.LI
The WRITE32 transaction takes no more than 12 NIO states.  This allows one wait state.
.LI
Arbitration takes one additional state.  This is required to meet NIO protocol.
.LI
When the cache is being dumped to main memory there is no other NIO bus activity
going on.
.LI
All other power fail activity takes less than 3 msec. (OS overhead and RTC updating)
.LE

This allows 512K bytes of cache to be dumped.

.DF
  (524288 Bytes/32 bytes per write) X 13 NIO states per write
  X 125 nsec per state = 26.6 msec.
.DE

The CPU must be able to send the PMI a cache line in the same amount of time
that it takes the PMI to write the cache line to memory (13 NIO states).
The synchronizer for the PMIN is designed to work with a CPU clock as low as
24 MHz.  Assuming that we want the cache dump to also work at this frequency,
the budget for the CPU side is 39 CPU states.  (The NIO bus is 8 MHz and so
13 NIO states take the same amount of time as 39 CPU states at 24 MHz.)

The following assumptions are made on the CPU side:
.AL
.LI
The instructions can be executed in 10 states.  The Firefox loop takes about
5 instructions with one taken branch.  The estimate for this is 6 states.
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There will be no instruction cache misses after the loop is executed
once.
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The total number of states including any overhead to do a copy out will not
be greater than 18.  The conservative estimate for this is about 16 states.
.LI
The PMI will buffer two cache lines to be copied out.  (The one being
transferred on the NIO plus one more.)
.LI
The overhead to do any synchronization that is necessary, to switch between
the copy out buffers and to release the CPU so that another cache line can
be received will not be more than 9 states.  The conservative estimate for
this is 5 states.
.LE

All the states used add up to 37 CPU states, which leaves two states margin.

