
April 12, 1985
Rob Horning
Weekly Update

I have pin plots of the RAM board to red line.  I hope to get started on
doing that soon.  This is taking second priority to the cache definition.
I am going to have the board made by photronics.

We are making progress on the CCU and TCU definition.  The definition
is being developed as a system.  The components (TCU, CCU, arrays) are all
being defined together.  I plan on having a write up of were I think we are
for the video conference Monday.

I have 25ns static RAM samples from Cypress.  I should get some from Toshiba
next week.  I am expecting some 20ns 1K by 4 RAM's from AMD next week also.
Ed Holland suggested that I go to California and visit Cypress along with some
him and some other people working on Cheetah.  I think that this would be
a good idea.  At the same time we should try to visit AMD.  Both are in the
bay area.  I would also like to get a better feel for Cheetahs needs so that
I can do a better job of representing there inputs on CCU and TCU definitions.
