
8/12/85
Rob Horning

I continue to work on the details of the SRAM timing specs.  I have
had some feed back from Cypress and Hitachi.  I think that all the
timing parameters are worked out.  There are still some concerns on how to
measure the timing relative to the output level.

I spent some time looking at what it would take to fit the memory chips
on the 8 Mbyte board.  I think that they will fit without putting the caps
under the chips.  I used spacings that I got from Larry Maple.  (His first
pass spacings did not look like they would fit but he took 25 mils off
each dimension.

I experimented with the Cypress SRAM driving a data line to verify what we
should have in the budget for delay.  Marlin Jones also ran an experiment
and got different results.  We have however agreed that the budget will be
about one nano-second.  I measured the RPN bus delay to be about 2 ns.
The budget is 4.5 ns.

