August 17, 1985
Rob Horning

The chips designers have decided that they want us to push to have
the data set up time be 10 ns.  I have asked the vendors to give me
feed-back on this.  The chips designers are still shooting for 15 ns.
I think that we have come to an agreement on how to measure the output
timing (in memo on 16K x 4 SRAM update).  Hitachi has changed there day
to be here to September 4 in the morning.  They will only be here for
an hour or two.

I have startered to work on the placement and termination of the SRAM
arrays.  I plan to terminate with both a series resistor and a diode.
I will make the address lines as low impedance as possible.  Just
resistors requires the value to be so large that the slow case is
marginal and just diodes is to high Q.  (The worse case condition does
not seem to be at the extremes).  I have done all my simulation using
an abbreviated model.  I am in the process of verifying that this matchs
the full model.  The parts placement could be optimized by moving at
least one of the PGA's but I think that I can make it work without moving
any of Lieth's parts.

