
July 19, 1985
Rob Horning

I have started to push for 2K x 8 25 ns SRAM's.  I have a a proposed
spec for the part.

I have continued to work on the CCU/TCU timing and have had to make some
changes to the spec.  I am pushing MTC to get the spec to the vendors by
next week.

The method for measuring timing had to be refined because Cypress had
some problems with it.

I have been do some SPICE modeling on a 16 RAM array (Cheetah cache).
It looks like we can pick up from .5 to 2 ns by changing the termination
and/or the layout.  More modeling needs to be done to verify this and
we have to show that it is feasible to layout.

