
Rob Horning
June 28, 1985

I found and fixed the problem with the memory tester.  The memory
board works.  It will work in battery backed systems because I
pulled the connector pins on the non-backed supply.  Arnold ran
a humidity test and RFI o the board.  Running the RFI test points out
a problem that I have been concerned with.  All the boards in the
system are running off of the same clock.  It is hard to tell what
is contributing to the problems and the large problems (CPU clock)
will tend to hide other marginal problems.  Arnold said that the
memory board may be contributing to the RFI problem.  He said that
he will do a scan without the CPU board to see if there is a problem.

I presented a proposal to Peter that we support 1 Mbit RAM chips
with MC-F.  He agreed and I sent a proposal to Denny Georg.

It looks like the 16K x 1 SRAM cache system will not be able to
to run at 25 MHz.  I think that I made it clear to Peter that we
have to assume that this is the system that we will introduce.
It is likely that we will have the 16K x 4 parts but we can not
depend on them.

I have been working with the chip designers on the write enable
timing problem.  They have agreed to use chip enable to prevent
bus contention (requires a pad).  This also makes the timing a
little easier to meet.  We are pushing the timing in this area
and we need to spend time evaluating it.

