
10/11/85
Rob Horning

I wrote a memo in response to the request for 20 ns SRAM's.  I pointed
out that there were some risks involved in trying to get them and that
it would not be easy to support both a 20 ns and a 25 ns SRAM.  I did
talk to Cypress about getting a 20 ns part.  They do not feel confident
that they will be able to get full spec 20 ns parts.  They think that
there is good chance that they could get parts if the voltage spec was
changed to 5.25 +-5%.

I am going to hold off on taking the 8 Mbyte RAM board into PC layout so
that I can get the math board ready to take in and take it in through.
I currently plan on going to PC layout 12/2.  I still need to look at the
pert to make sure that this is soon enough.

I am reviewing and making some changes to the CIO clock/delayed clock
circuit to make sure that it works and that it can still share a delay
lone with the PDH.  I think that it can be designed to work with a full
10 MHz MID_BUS. (This is not a must.)

There were some misunderstandings about how the SIU maps addresses to
the PDH.  We worked these out and I changed a PAL and added a couple
of jumpers to the PDH board to fix the problem.  We also redefined
the LED register and I wired a connector to hook up the LED's.  The PDH
seems to be working.

