11/16/85
Rob Horning

I am 90% done with the changes to the PDH.  I have started to work on
the schematic.  I have worked on the following areas:
  
  MID_BUS timing - The PDH and CA will be able to share the same delay
  line.  They are both designed to run at 10 MHz on a full MID_BUS.
  I have asked for some samples of a custom delay line that I specified.
  I should get them in 2 to 3 weeks.

  RTC battery isolation - I made some changes to this circuit to give a
  little more margin on undershoot.  I also changed the transistors to
  the same one I want to use in the write protection circuit.

  Write protection - The RTC/EEPROM write protection circuit was changed
  so that it would be faster.  It was also simplified a little.  I MRTed
  some transistors to test the circuit and the RTC isolation circuit.

  EEPROM - I have requested some samples of a couple of EEPROM's.  I plan
  on using a 2K x 8 part.  There is an 8k x 8 part that is pin for pin
  compatible.  I will design the PC board so that it can use both.

  Crystal - I have started to look into what will be needed for a crystal.
  I still need to choose one.  I will need to decide before going into PC
  layout.

  ROM - The PDH will support two ROM sockets.  These can hold 512K EPROM's 
  or 1 Mbit ROM's.  A jumper will be used to choose the size.


