
10/18/85
Rob Horning

We are meeting every Wednesday to discuss the CCU timing problems and
simulations.  The Cheetah guys say that they will have there simulations
done by next week.  Based on there preliminary results and on some
simulations that I have done I feel that we will end up with positive
margin.  Mark Ludwig told me that he is meeting his budget on the SPL
very easily.  I wrote a program to calculate margins and optimal SPL
edges given the simulation results and RAM specs.

Leith has said that he would move the one CCU down to give more room for
the RAM's and allow a more optimal layout.  However I figured out a way
to get a fairly optimal layout without moving the CCU.  I have run some
simulations that show much improvement.  I have layed out most of the
array but still need to hook up the data lines.  I am using 150 ohms to
VDL for termination.  This takes less than .75 watts which should cause
no problems.

Lattice will be here at 2:00 on October 28 (1LT2) to discuss there company.
They plan on having 2k x 8 25 ns parts in production in January.


