
9/14/85
Rob Horning

I spent almost all my time working on the cache SRAM array timing.
I think that we have a solution that will work.  All of the
improvements are coming from the NMOS.  The two main areas that
are being improved are the placement of SPL edges and the method
for measuring worse case timing.  SPL edges will be placed with
+ or - 1.5 ns accuracy.  The method for measuring worse case
timing has been changed to state that if a chip has the worse
case slow driver then the fastest driver on the chip will be
nominal (worse case fast chip will have the slowest driver be
nominal).

I got the 2K x 8 spec from Lattice and it looks good.  There was
only one spec that did not meet our needs.  I talked to them about
it and they will get back to me.

