
9/20/85
Rob Horning

I looked at a couple of more ways of improving the CCU timing and we
reviewed our method for measuring timing.  The Cheetah guys are going
to have to do several of there simulations over because of the new way
of measuring timing and because there were some mistakes in the
simulations that they did.  I have asked them to do a couple of the
critical lines first so that we can get an idea of what the total
margin will be.  They still do not have all the driver models that
they need.

I send out an update to the vendors on the SRAM specs.  Most of the
changes were relaxations that vendors had asked for.  I also added
several specs to cover things that are not currently specified.

I made a circuit to look at the Hitachi 16K x 4 SRAM's.  I accessed
them in a few different ways the slowest address access time I saw
was about 15 ns.  This was with vcc set to 4.5 volts.

I have continued to look into Lattice.  I found out that they do not
have there own production facility.  There parts are built by VLSI.
They plan on having there own fab in about a year.  Hal Good is getting
a Dunn and Bradstreet report and I have asked the salesman to send
me information on the company.  I also asked him to send me information
on how they will control quality and what they will do if the market
turns up and VLSI does not want to continue to build there parts.

I have been in contact with NID (Nothwest IC Division?) and they are
interested in providing us with some of the parts that we need.
They are most interested in the 4K x 4 part.  I sent them the spec and
the spec update.

I updated the RAM section of the ERS to reflect the fact that there
will not be a 1 Mbyte board and there will be an 8 Mbyte board and
maybe a 16 Mbyte board later. 

