
12/8/86
Rob Horning

I reviewed the MID_BUS timing spec for the CA chip and attended a design
review.  I did not see any major problems.  There are a couple of small
negative margins on a fully loaded 10 MHz MID_BUS.  The chip tape released
last week.

I have continued to keep on top of what is happening with the SRAM's.  I
have been told by Jim Couts that we can get the SRAM's that we need from
Hitachi.  Toshiba has said that they will be able to give us all the parts
that we need by the middle of January.  Jim Couts will test the parts
that he got from Toshiba and let me know this week how they look.  I will
be visiting Cypress this week to see how they are doing.  They are supposed
to have 1000 parts for us (I think that this may slip a little).

I started to prepare for a meeting  to discuss memory architecture issues.
There are a few changes proposed that I think should not be accepted.

It looks like AMD has an EEPROM that will be able to replace the one that
we have now with no changes to anything.  It is an 8K byte part, but we
will only use 2K bytes.

I got a JEDEC disk for my PAL's.

I helped prepare for the YEW visit.  Tom Spencer ended up taking care of
them because I had to leave town.

