
2/7/86
Rob Horning

I have started to look at the TCU arrays.  I am comparing the board to
the simulations.  The board had a slower fall time than expected.  Most
of this seems to be caused by the SRAM address line having a much higher
capacitance than expected.  I am sending Toshiba a part to evaluate.

Toshiba has seem first parts on there new process and are not getting
the yields that they hoped for.  They will keep me updated on what the
problem is.  There could be a problem with getting parts from the new
process in March.  They will be here on February 20 to discuss the part
and also the 1 Mbit DRAM.

Sang Park of the MTC has expressed concern about us using 25 ns parts.
He did not quantify his concerns very well over the phone.  He would
like to get together to discuss our strategy for SRAM's and also 1 Mbit
DRAM's.  I am trying to set up a meeting here on February 7.

Loveland has been having trouble plotting the Math board.  I am not sure
when we will get board.  I am calling them every day.

The extender boards should go to Boise Monday.  They have to be plotted
on Boise because our photo plotter cannot plot fill that large.

Hitachi told me this week that they plan to supply us with about 100 or
200 samples of 1 Mbit chips (SOJ 120 ns nibble mode).  These should come
in April.

