
1/31/86
Rob Horning

I have finished checking the math board and have sent tapes to Loveland.
They are going to plot the film because this allows them to compensate
for there process.  Tom Spencers design rule checker found several
problems.  One of them is a problem that we also have on the CPU board.
We try to place traces on a half mill grid when we go two between on
PGA pins.  The Gerber format does not allow this and so all of these
traces are moved by .5 mils.  This causes a design rule violation.
We have not decided how to fix the problem.

I have finished the 8 Mbyte schematic and run the list connector with no
errors.

I updated the power estimates and gave John Hoppal a copy of the board
blank with the power of all the chips.  The power estimate is 25 to 30%
lower than the budget.  I also updated the parts list.

I talked to Stantel.  They are going to try to get us some 25 ns parts by
March.  I sent them the latest updates to the specs.

Toshiba called and said that they may want to have some spec relaxations
the parts that they deliver in March.  I told them that we may be able to
relax the voltage spec but temperature would be a problem.  He is going to
get back to me on this and also let me know when they think that they will
have parts for MTC to qualify.
