
July 21, 1986
Rob Horning

I had 14 more math boards built and so now we have 24.  I plan to build 8
more when we have all the VLSI.  Most of the boards have the voltage
regulator and have been turned on.  They have all been turning right on.

I looks lie the CA will be moved to a 272 pin package.  This will mean a
few days work for me and a larger change to the PC board than I would like,
but the change is needed and so we did not fight it.

I figured out what the problem is with the parallel card is.  The MC-F and CA
chips have the same problem.  They all need a clock to get to there reset
state, the SIU does not provide a clock until a little before PON goes high.
There is about 500 msec. with power but no clock.  I have seen the parralel
card and the memory card driving the bus at power up.  I think that adding the
CA made the conflict even worse.

There is a meeting on Wednesday with Dave James and his gang to talk about
memory architecture.  It is planned to be a phone conference, but I am going
to see if the video conference room is available.

Cypress called and said that they think that they will be able to get me
enough real 25 ns SRAM's to build on CPU board this month.

There is a problem with MC-F that will not allow us to raise the MID_BUS
frequency to 10 MHz.  They are hoping that they will get some faster parts
out of the next run.

I have been spending some time with Jim turning on RAM boards.

Jeff was seeing memory data lose during power fail, but it is not clear if
it is the memory board or the MID_BUS tester that fails.

