
10/6/86
Rob Horning

The delay line for the memory board is going to be 21 ns.  The simulations
and experiments showed that there are no big problems with having the delay
round trip being greater than the high or low time.  Photronics said that
they could keep the e sub r to 4.6 plus or minus .2.  This
gives .5 ns accuracy for the delay of 21 ns.  I changed the memory board
theory of operation to incorporate these timing changes.

Because of the problems with MC-F I called the CA designers to verify that
we did not have a problem there.  It turns out that we have a worse problem.
The way that they do the timing does not allow us to use the delay line to
prevent a buffer conflict.  They believe that it is okay to have a buffer
conflict when one part is turning off as the other is turning on.  I would
like to see then leverage what the MC-F did.  I will keep in touch with them
to make sure that they continue to work on the problem.  There is a video
conference Thursday with this as one of the concerns.

I released the math PC board.  We are not getting proto boards.  We had a
meeting with the 3065 test people and they said that they could bet by with
the current board to turn on there tests.  I told them that I would get the
information on how to turn off the CA chip and how to do a basic test to
find out if it is inserted the right way.

We met with Hitachi last week.  They were going to slip the delivery of the
1 Mbit DRAM's until we told them that we needed them in 2 days.  They got us
the parts from Japan in 2 days.  They can get us 100 2K x 8 25 ns working
samples by the first week in November.  They can get us 350 full spec parts
by the end of November.

Cypress did not get any good 2K x 8 parts from their new process.  They said
that this was because the wafers went bad when they held them up to evaluate
the problems they were having and to make the laser repairs of the mask.
They still expect to meet there commitment to get us the parts we neeed in
November.

Some of us met with some people from FEO to discuss what we wanted to see as
PC design features to help us simulate the PC board as a circuit element.
I do not expect to see any great improvement over what we do now in the near
future.  We told that what we needed was good interfaces to other design
systems.

I spent a good part of my time on ultra fox.  We met with Les Walker of TWO
marketing to discuss servers.  He was not sure how to sell servers.  He needed
a good way to measure how performance would be improved by using a server.
As a follow up I got everyone copies of Ken Sandbergs paper on servers.  We
need to understand how servers effect ultra-fox and if ultra-fox should have
a configuration that makes it a good server.  Tom and I met with an SE to
get his inputs on 1990 workstations.  He wanted to see us doing more high end
stuff.  He did not think that there was a future in workstations.  We need to
talk to someone who is more up on selling workstations.

