
10/20/86
Rob Horning

I prepared for and went to the design review for the CA chip.  I have not
started to set up the delay new delay line because the timing still seems
up in the air.  He has been reset on his driver design.  Most of the people
at the design review thought that his current design was high risk.  He may
change to the SIU driver.

I checked the film for the math board.  It went to Loveland on Wednesday.

Sang Park was here Wednesday.  He is still concerned about the 2k x 8 parts.
He is very willing to give us any help that we need.  I will go with him 
and Jim Couts this week to meet with Hitachi, Toshiba, Cypress, and VTI.

Cypress expects to have 2K x 8 samples in about 3 weeks.  They told me that
they did manage to get about 40 parts out of the run that went bad.  I will
talk to them about both of these things when I am there this week.

The parts from VTI look like they really are 25 ns parts.  There is one problem
with the part but, they new about this and are fixing it.

I spent about a day looking into TAB and writing up a first pass spec.  There
are a lot of holes to fill in the spec, but it is a start.  I now have a good
idea of what goes on with TAB.  There are still a lot of concerns to resolve.

I set up all the meetings with the people in Cupertino that we want to talk
to about ultra-fox.

We met with Ken Sandberg to talk about servers.  He had a lot of good data on
servers.  One concern that I have after talking to him is getting good MP
software technology.

