
Rob Horning
12/14/87

I made some slides for John Doyle's visit.  These  were of the layout, showing
the critical busses and thermal distribution.

I put the receiver together with a model that we came up with for the ECL
driver and the PC board.  I have argued with Rich Luebs a lot on how to
distribute the clock timing budgets.  Combining the simulation eliminates
the distribution of budgets.  It does not look like we will meet the goals
for clock skew and delay, but we are close.  There are some things that
we can do to improve the timing and we may be able to relax the spec
some.  We should get some fairly good first pass specs this week.

I met with Paul Bodenstab, Rich Luebs, and Tony Riccio to establish what
needs to be done to finish up the clock spec.  Paul is going to run the
simulations to come up with some first pass specs.  I gave him some conditions
to use for the PC board and ECL driver.  I will verify the worse case
conditions for the PC board and ECL driver.  It is not clear what the
worse case conditions are.  Tony will verify the the models for the ECL
driver are good.  He will also work on getting a better spec.

I have continued to give people models for the PC board.

