
I have continued to model the ECL driver.  I reduced the wire bond cross
talk by a factor of 4 and things worked a lot better.  I met with Rick Luebs
and Paul Bodenstab to discuss the budgets for the clock.  At the time I still
had a lot of concern with meeting the budget.  My biggest concern was with
getting reasonable ECL levels out of the CMOS driver.  This is less of a
concern now because the ECL clock buffer does not appear to need ECL levels.

I got the new cross talk models from Dave Quint.  They look much better.
Most of the noise will be common mode.  He did leave one line off, but said
he would get this done today.

Paul Bodenstab has suggested that we not use the ECL buffer.  This would cost
us about 10 PAD's on the CPU.  We could get these.  There are a lot of reasons
why this would work better and would be lower risk.  The biggest problem is
that it is a change, and we may be opening a new can of worms.

I have been talking to Tony about the ECL driver specs.  It looks like the
part will work well, but we still need to spec it.  The only spec we have is
for regular ECL parts.  We need to develop a spec for this part.  I have
started to work on this.

I looked at what it would take to mirror the layout.  This does not look like
it would be a big problem, but there are some risks.  The CPU and CMUX
pinouts can still be changed.  I think that it would be a mistake to pre-heat
the air to the CPU.

