
Rob Horning
2/8/87

I spent most of the week looking at SRAM outputs and running simulations
with the Hitachi output model.  I had some trouble getting them to match.
There was a problem with the model that I fixed and things matched better,
but there are some things that do not match well.  The real part seems to
act like a tuned circuit in that the output high level changes depending
on the load.  AC load changes cause the DC level to change.  This makes it
difficult to come up with a good output model that covers all cases.  I
think that I will make a couple of simple spec additions and then use these
to come up with estimations of delay and hold time.  I think that we can
still meet all the budgets except for data tag delay, which I have been
told is ok.

I talked to the CPU and CMUX people about pinouts.  There has not been major
changes to the busses.  They told me that they can keep the clocks in
symmetrical places.  I took the CPU clock padout and gave it to the CMUX
people and asked them to make it the same.

I looked at the parts placement with John to try to come up with a better
thermal placement.  We could not come up with a significant thermal
improvement without causing major electrical problems.  We plan to just do
some small changes to the the current parts placement.  The bus connecting
the Bit chips will probably get longer.

I set up a meeting with Andy Vogen and some of his people to talk about
our surface mount concerns.

