
1/4/87
Rob Horning

I finished up the simulations for the clock.  I used the worse case PGA
model.  It did not cause large problems.  Tony gave me improved values
for input capacitance to the ECL driver and this more than made up for
the worse case PGA models.  The simulations show that the clocking scheme
will work.  The clock timing does not meet the original budgets, but
the budget can be increased if some fixed delay can be added to the SRAM
access time.  If we use the fastest SRAM's we will need to add delay to the
address lines to improve the hold time unless we can improve the hold
time spec for the SRAM.  This should not be a problem.

I started writing up a summary of the results of the clock simulations.
When I finish this I will go over everything that I did with Tony Riccio,
Paul Bodenstab and Rick Luebs to make sure that all my assumptions were valid.

Howell needed to know what our SRAM needs were and so I came up to date
on the latest CMUX changes.  We are using one less SRAM than we used to
use.  This is because one less parity bit is being used in the tag
of the instruction cache.  It only saves one SRAM because the array that
contains the off chip TLB needs a few extra bits.

I took 2 days vacation plus there was the New Years Holiday.

