From maj@hpesmaj Wed Jan 18 15:08 MST 1989
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From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8901182210.AA07533@hpesmaj.HP.COM>
Subject: new tools tomorrow morning
To: lab@hpesmaj, willy@hpesmaj, paulf@hpesmaj, annika@hpesmaj
Date: Wed, 18 Jan 89 15:09:55 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
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Status: RO

To: Lab
From: Mike Jassowski
Re: New tools

   Tomorrow morning (1/19) I will update the tools--Really.  Appended is
   a list of all of the changes to be made:
--
		-Mike Jassowski

12/20/88 hbdcb_man (Harlan Talley et al)
    - new installation information
    - naming conventions updates and ERC properties
    - updated schematic and artwork introductions
    - artwork verification updates
    - updates on library management utilities
    - new chapter on spice combining system information, information
      from the HPSPICE manual, and information from assorted memos.
    - updated chapter on AWSIM
    - tutorial on FUNGEN schematic to artwork conversion
    - updated chapter on system administration
    - miscellaneous minor changes

12/20/88 terminus (Harlan Talley)
    - added Whatstrings to mgr and FUNGEN.

12/20/88 terminus (Harlan Talley)
    - added 'system' function to FUNGEN.  Function allows you to execute
      a command in the periphery (or Unix) shell and, optionally,  return the results
    to a string variable.
    - added the 'aliasof' function which returns the alias of a string in the 
      context of the current set of aliases.
    - Fixed bug in FUNGEN which left a leading character off some variable
      names in the trace file.
    - Added test for names which alias to a NULL signal names.
    - Changed blockname check to test for a maximum length of 10 characters
      and to accept a starting characte of lower-case z.

12/20/88 fungen (Harlan Talley)
    - Add no_hbd option which will run FUNGEN without creating piglet data
    - Changed the -d option to not ask about running schematic conversion 
      program.

12/21/88 module generation (Ed Weber)
    - Updated following binaries to 1.2-2cr versions:
	-kiss
	-plagiarize
	-plagmain
	-trmacro
	-terminus (compiled in CICD)

12/28/88 Pla Generation (Ed Weber)
    - blindfold updated to latest version.
    - corrupt logic warning message removed from foldpla script
      due to blindfold fix.

12/29/88 [cmos34,cmos26]/guide.cbm (Rich Nash)
    - Updated to latest version - misc. minor changes - Does not affect data.

1/2/89 installation (Jim Moy)
    - The CheckSpace script which is run during the ninstall process now
      uses "bdf -t hfs" instead of df so it doesn't get hung on bad nfs
      connections.

1/2/89 Module Generation (Ed Weber)
    - tran2hbd script modified to use cb2bdl instead of modgen_bdl script.
    - script $CBROOT/hbdcb/lib/modgen_bdl DELETED.

1/4/89 piglet, xpiglet & x11piglet (Alexander Elkins)
    - Fixed piglet to compile under HP-UX 6.2 (pc & starbase changes)
    - Fixed ADD command prevent reference cross names from being
        treated as instance when a device can't be loaded or a
        reference cross has not been declared.
    - Modified ADD command to turn off rubber-band tracking when input
        is coming from a file.
    - Fixed ADD command to update reference cross position when it is
        stretched during the add process.  Problem was that once
        streched, a reference cross was displayed in one place and had
        to be picked from its original position.
    - Fixed ADD command to require that an instance name must be specified
        before the :Step option can be specified.
    - Fixed display routines to draw a dot if an instance is smaller
        than a pixel instead of nothing at all.
    - Added a :P<number> option to the WINdow command to allow the user
        to specify the minmum number of pixels of dimension size an
        instance must have before it will not display as a single dot.
        The default is one pixel.
    - Fixed the echo log file to be line buffered instead of fully buffered.
        This means all commands will immeadately show up in the echo
        log file as they are typed.
    - Fixed grid to work in x11piglet.
    - Implemented emacs ksh command line editing mode.
    - Fixed ADD command to not look for two same points in succession
        and treat them as end of command.
    - Changed the list command to display the grid line option setting.
    - Fixed to save the grid line option setting in the piglet.db.
    - Fixed the CHAnge command to handle editing notes with imbedded
        line feeds.
    - Fixed local edit-in-place to copy all of the old device's
        parameter settings.
    - Fixed group/wrap to copy the current device's parameters, i.e.
        logic level, grid settings, lockangle, etc.
    - Fixed the hazzard which occurs when a local edit-in-place
        edits a new device and the device is saved during the edit.
    - Changed note editing to go to the command mode rather than the
        insert mode (popular demand).
    - Fixed keyboad input to be accepted when a mouse pick is made in
        the X10/X11 graphics window.
    - Fixed keyboad input to be synchronus with mouse picks in the
        X10/X11 graphics window.
    - Added SYSTEM_CURRENT_REP and SYSTEM_CURRENT_BLOCK for use with
        the SHEll command (pdn).
    - Upgraded to use the new NFS/DTS routines from DTC which now make
        use of the remote semaphore deamon to do path translation.
    - Fixed plotting child process to not close the X10/X11 window
        sockets -- this was causing plots to hang.
    - Implemented SAVe :T <map_file> <device>.  Map_file is parsed to
        determine which layers and classes to input into the Trantor database.
        Instances are always input.  Rectangles are input as separate
        area shapes with only one rectangle hanging off of each shape.
        Notes are added as text hanging off of classes.  Polygons which
        are stretchable or non-orthogonal are added as ploygons, all
        others are boxerd into area shapes with multiple rectangles hanging
        off of them.  Circles, ovals, and text components are converted
        into polygons on a one hundredth mircon grid, stretch information
        is lost.  Zero width lines are input as lines.  Lines with width
        are input as polygons, stretch information is lost.  In general
        the full functionality of pigin is implemented, with the exception
        of some odd flags having to do with archive.ext file data.  Also
        note on masks for which there is no layer being input on the
        same mask is left floating, otherwise it is attached to the layer
        being input on the same mask.  Text is converted using whatever
        is specified as a shape in the TEXTDATA file read in by piglet
        as opposed to the hard coded shapes in pigin.
    - Implemented EDIt :T <map_file> <device>.  Map_file is parsed to
        determine which layers and classes to output from the Trantor
        database. Instances are only output if either a layer or class
        is mapped for output to mask 0.  All rectangles hanging off of
        area shapes are output as rectangles.  Points hanging off of
        a polygon shape are output as a polygon.  Points hanging off of
        a line shape are output as a line.  Text hanging off of classes
        is entered as notes, regardless of attachment.  Only instances
        which are realies or pieces are output.  In general the full
        functionality of pigout has been implemented.
    - Added 'R', 'P', and 'S' options to LISt.  'R' selects realies,
        'P' selects pieces, 'S' selects "/<rep_type>" suffix.  These
        options allow the listing of the current devices children, thereby
        avoiding the need to process archive files for the information.
    - Changed INPut to accept the full descriptor complement of
        [component_type[mask]] [.component_name] [@signal_name] for
        selection.
    - Enhanced the change command to allow changing a text component into
        one or more polygons depending on the shapes specified by the
        TEXTDATA file.
    - Changed $FILES and PURge commands to check for write access and ask
        for permission to proceed if no there is no such access, before
        purging any file.
    - Fixed TRAce command to work correctly for components which have
        a component name but no signal name.
    - Changed to use rgb_to_index() starbase call instead of hard-coded
        color indicies.  This means the color index will chosen based
		on the one with closest mathching rgb value.  This may effect
		the actual color shown as well as when colors overlap.

1/5/89 PLA Generation (Ed Weber)
    - terminus/trio changes:
	- bit line coupling check fixed to include both sides of connected split
	- bit line folding improved to reduce term line length
    - Created script tran2pig to convert trantor.db to piglet.db using
      new features of piglet
    - plagen script modified to use tran2pig
    - tran2hbd script modified to use tran2pig

1/5/89 piglet_cmap (Alexander Elkins)
    - Created this script for setting the color map entries since piglet
        no longer automatically does this.  Its use is optional.

1/5/89 make_hcmp [cmos26,cmos34]/hcmp.cbm (Craig Heikes, Rich Nash)
    - Fixed a bug with long blocknames
    - Added -v option for verbose hcmp output.

1/5/89 scawsim (Craig Heikes)
    - Speed enhancements

1/5/89 art.map (Paul Nuber)
    - Added instance classes to cmos26 and 34 mapfiles for piglet.

1/6/89 
    - Release 1.17a+28

1/6/89 get_color (Alexander Elkins)
    - Released (initial version)

1/6/89 PLA Generation (Ed Weber)
    - Scan path buffer placement bug fixed. CTGzb01956

1/9/89 cmos34 ART.MAC (Paul Nuber)
    - Added missing error layers to display macros.

1/9/89 piglet, xpiglet & x11piglet (Alexander Elkins)
    - Added :C option for use with EDIt :T mode, assigns trantor layer/class
      name to component name, for use in error extraction.

1/9/89 start (Alexander Elkins)
    - Added :T option for starting trantor sestion
    - Added X11 not implemented for those that aren't yet.
    - Added defect workaround for stty EOF in hpterm for xpiglet invocation

1/10/89 h3run.cb (Steve Herbener)
    - Made fix for the PLOC numbering problem on busses. This was the
      one where if you put a PLOC (Port LOCation) property on a bus,
      each indiviual bit would get the same PLOC value - great if you
      want everything shorted together.

1/10/89 art_archive (Paul Nuber)
    - removed 8 character name restriction for DRC.

1/10/89 piglet_cmap (Alexander Elkins)
    - Fixed the green value for the SkyBlue color index entry.

1/11/89 tran2pig (Ed Weber)
    - Changed to set schematic symbols at piglet LEVEL 2

1/12/89 terminus/trio (Ed Weber)
    - Empty columns now automatically inserted to relieve bit line
      coupling problems in PLA array.
    - Improved post-blindfold bit line folding.

1/12/89 mk_harp_xref (Tom Walley)
    - mk_harp_xref, which creates a flat harp name to hierarchical name map,
      is called from the h3run.cb.

1/12/89 piglet, xpiglet & x11piglet (Alexander Elkins)
    - Fixed HPWINDOWS and X10 cursor to use GXxor with Black <xor> White
      as a value while tracking, as a result is no longer necessary to
      set color index 55 on a 6 plane display, also the cursor is more visable.
    - Changed X10 and X11 cursor from 15x15 to 17x17 pixels, the same size as
      the one in HPWINDOWS.
    - Fixed non-CB mode to not use rsemd for path translation (Paul Ilgenfritz)
    - Removed unlink() prior to rename() for piglet.db write.
    - Added UNLINK_BEFORE_RENAME environment variable to cause an unlink()
      prior to a rename() for backward compatibility with HP-UX 5.5 (Paul I.)
    - Fixed a defect in the piglet.db write proceedure which caused a
      corrupt piglet.db to written.  Odds on this happening are 1000000:1.
      Only one character is corrupted, a record identifier, causing the
      read procedure to abort at that position in the file. (Paul Ilgenfritz)
    - Trailing '/' have been removed prior to look-up and caching in the
      path list to minimize similar entries and performance degredation.
    - Fixed a defect in the trantor.db extraction proceedure which caused
      an abort when a stretchable component was processed.
    - Fixed plotting in HPWINDOWS which was deadlocking the window system
      upon forking the process to begin plotting in the background.
    - Fixed incorrect drawing placement of child devices inside of a
      child device which were smaller than a pixel.
    - Fixed FILES command to not ask "Device exists on disk, purge (y/n)?".
    - Fixed a defect with the DEFine <macroname> command which was hanging
      when an attempt was to undefine the macro using a null string ("").
    - Fixed the GRId command which was displaying improperly when the
      "Largegrid=1" was used and the value was not unity.

1/13/89 ZMIND0, ZIND0 (Rich Nash, Craig Heikes)
    - New primitives for mutual inductance
    - PRIMITIVES MUST BE UPDATED IF YOU PLAN TO USE MUTUAL INDUCTANCE
      IN SPICE.

1/13/89 Scip Changes (Craig Heikes)
    - all: added new string types for 800 compatibility
    - scformat: added a new bdl parser and a mutual inductor primitive
    - sccompare: added a new bdl parser
    - scawsim: fixed the missing awsim db problem

1/13/89 hcmp loop (Mark Hammer, Craig Heikes)
    - added a command artbdl2hcmp which replaces unnamed signals and 
      instances with the proper hierarchical names for harp blocks.

1/13/89 capval.exe and sigcap.exe (Craig Heikes)
    - added a new bdl parser

1/13/89 piglet, xpiglet & x11piglet (Alexander Elkins)
    - Fixed unterminated menu bug which caused a menu entry to randomly be
      terminated by white space even though the entry in the menu didn't.
    - Fixed the graphics window to go away when exiting piglet with plot
      still running in the background in X10 and X11.

1/13/89 (friday)
    - Release 1.17a+29

1/16/89 scformat (Craig Heikes)
    - fix bug with flattening primitives like NANDS and NORS
1/16/89
    - Release 1.17a+30

1/17/89 DRC (Paul Nuber)
    - Changed art.cbm for fast DRC to rebuild trantor.db's for pieces
      if piglet.db is newer.
    - Added rm_dup_mess to remove old messages left in log files.
    - Installed new, faster pigin from DTC.

1/18/89
    - Release 1.17a+31

From ren Wed Dec 21 13:58 MST 1988
Received: by hpfclr.HP.COM; Wed, 21 Dec 88 13:54:49 mst
From: Bob Naas <ren>
Full-Name: Bob Naas
Subject: Finding Floating nodes in AWSIM
To: lab@hpfclr
Date: Wed, 21 Dec 88 13:54:45 MST
X-Mailer: Elm [version 1.7]
Status: RO


 I have written a short program that finds nodes that are connected
 only to gates in an AWSIM fet_file.  This has been exceptionally useful
 to me for finding signals that are not connected without having to
 go through the pain of debugging AWSIM failures.

 If you are interested in this program, drop me a line.

 Bob Naas

From jpl@hpesjpl Wed Dec 21 17:43 MST 1988
Received: from hpesjpl.HP.COM by hpfclr.HP.COM; Wed, 21 Dec 88 17:43:14 mst
Received: by hpesjpl.HP.COM; Wed, 21 Dec 88 17:47:12 mst
Date: Wed, 21 Dec 88 17:47:12 mst
From: Jon Lotz <jpl@hpesjpl>
Full-Name: Jon Lotz
Message-Id: <8812220047.AA03687@hpesjpl.HP.COM>
To: lab@hpfclr, ren@hpfclr
Subject: Re:  Finding Floating nodes in AWSIM
Status: RO

Lab:

 I too have written a program that finds floating nodes and floating gates. 
 The program that I wrote also checks for inverters that don't drive any
 gates, and floating inputs to transfer gates.  I guess I should have
 told Bob about this program sooner...  

 On the subject of awsim, I also have written a "Better" awsim post 
 processor that allows one to look at buses in hex, and even allows
 one to output the state of regester that have "internal bus notation"
 ( for example: /INSTANCE/REG[0:31]/BITSLICE/DPREG1 ).  The output of
 the program is alot easier to read, and the program is considerably
 faster than the post processor that comes with the scip tools.

	    Jon Lotz


From maj@hpesmaj Fri Dec 30 10:37 MST 1988
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Received: by hpesmaj.HP.COM; Fri, 30 Dec 88 10:39:03 mst
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8812301739.AA17883@hpesmaj.HP.COM>
Subject: It's tools time again...
To: lab@hpesmaj, willy@hpesmaj, paulf@hpesmaj, annika@hpesmaj
Date: Fri, 30 Dec 88 10:38:56 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: Tool update

  Lots of good stuff this time since we are three releases behind...
A brief overview of some interesting stuff:

  * A fix to make_hcmp (hierarchical bdl compare with pattern matching).
  Can be used to bdl compare standard cell blocks, or any other block.

  * Lots of PLA updates (smile Dan).

  * Mold stripped signal fix.  Now tells you the REALNAME of the striped
  signal.

  * Best changes.  BE SURE TO READ THE NOTE BELOW if you use Best.

  * Property addition to make_drc.  You can now attatch properties to
  blocks, and even cause a blocks ports to not be automatically
  promoted.
--
		-Mike Jassowski

12/6/88 waiver (Paul Nuber)
    - suppressed error messages about temporary files

12/6/88 make_hcmp (Rich Nash)

12/6/88 fungen 
    - Fixed linking for bdl option
    - Added -no_hbd option to not make piglet data
      (sets tran_src_time flag to make trantor.db the src)
    - Fixed -d option to not ask if it should rerun sch_to_art

12/6/88 PLA Generation (Ed Weber)
    - Added -no_hbd option to plasticks script
    - Created new terminus script buildpla.  This script will build
      the sticks diagram and full artwork with just a blockname 
      argument.  It expects the source files to be in the modgen
      directory.  A man page will follow later, but options are
      now commented in the script ($CBROOT/hbdcb/scripts/terminus/buildpla).

12/7/88 terminus (Harlan Talley)
    - Fixed bdl option to correctly handle indexed instances
    - Improved access functions, based on Ed Weber's profiling results,
      will significantly improve performance of fungen and trio (plagen).
      Trio performance improvement appears to be > 2X.
    
12/7/88 hbdcb_manual (Harlan Talley)
    - Released a soft copy of the latest revision.
      ADDITIONAL UPDATES WILL BE MADE SOON

12/7/88 mold (Steve Herbener)
    - Fixed error/warning messages from the "nodangle" and
      "esl_nodangle" transformations so that they write out the
      hierarchical names of signals/instances instead of the
      random-looking auto-generated names.

12/8/88 espresso (Ed Weber)
    - Newest release installed.  Seems to produce slightly better results.

12/8/88 artwork system (Randy Fiscus)
    - Fixed a defect in the non-circuit verify path

12/8/88 make_hcmp (Craig Heikes, Rich Nash)
    - Changed hcmp_filter so that make_hcmp will work with new fet naming
      in the artwork.

12/9/88 
    - Release 1.17a+25

12/13/88 (Randy Fiscus)
    - Fixed art_nonckt_drc showstopper bug.

12/13/88 
    - Release 1.17a+26

12/12/88 make_drc (Jim Moy)
    - Fix trantor core-dumper in artwork instance-naming.

12/12/88 ZENH0/bdl & ZPENH0/bdl (Tom Walley)
    - Removed the bdl rep of the above 2 primitives

12/12/88 cmos34 piglet configuration (Paul Nuber)
    - Removed reference to color Blue in process file that was changing
      color map.

12/12/88 guide, best_truth.3.o, bestfunct.3.a, model_main.3.o (Steve Herbener)
    - Installed the 1.2-2TC version of the above four files. This represents
      an effort to bring our binaries into sync with DTC. Also, these fix a
      BEST simulator scheduling bug that the UCIC folks saw, and the virtual
      memory utilization is much more efficient than in our current version
      of guide.

      ######################################################################
      # This update will force RELINKING of the BEST model.3 files (the    #
      # executable file that represents your behavioral models during the  #
      # simulation). IT WILL NOT force recompilation of your MADL source.  #
      ######################################################################

12/14/88 mkcub, _cubblock, travis, pathtrans (Rich Nash for Dave Pinsky)
    - Added new options to mkcub -a -A and -B for awsim, awsim with artwork, and
      best simulation type cubbyholes.  -a just gets sch and sym, -A gets sch, 
      sym and art, and -B gets struct, sym, and beh or sch 
      (no sch if beh exists).
      This minimizes the time and data for these type of cubbyholes.

12/14/88 conv_bmfiles (Rich Nash)
    - In certain cases some files would not be moved to the block_mgmt
      directory.

12/14/88 [cmos26,cmos34]/guide.cbm (Rich Nash)
    - Changed ls to /bin/ls to handle an alias problem.
    - Fixed compile problem related to structural madlc. Prior to the fix
      makemod had to compile the structural block to determine the 
      children blocks. If the ports didn't agree the log file contained
      errors about mismatched port definitions. With the new version of
      madlc makemod can parse w/o compiling the structural block to determine
      child blocks. Thus, child blocks are now compiled prior to the
      parent structural block. This fixes a problem Colorado Springs
      users had with the model building process.

12/14/88 PLA Generation (Ed Weber)
    - One sided PLAs now supported (terminus).
    - Bug with cmos34 I/O driver placement fixed (terminus).
    - make_logrep triorc parameter removed (terminus).
    - -no_art and -no_sim switches added to trio, plagen, buildpla
      to suppress artwork and BDL generation respectively (terminus,
      plagen, buildpla).
    - Scan path ports of I/O blocks now named <bus name>_<block name>_IN
      and <bus name>_block name>_OUT.  This keeps the I/O driver stack
      ports constant through driver addition/deletion (terminus).
    - Finish time added to buildpla log file.

12/14/88 awvec2cb, bdltocb, madlc (Steve Herbener)
    - Fixes to routines in two object code libraries that are used
      in common for a lot of DTC supplied binaries caused awvec2cb,
      bdltocb, and madlc to be recompiled and updated.

12/15/88 bdl.mapfile (Tom Walley)
    - Added parameter names such that spicepath required parameters can
      now be in a trantor.db created from bdl by bdltocb.

12/15/88 make_drc (Jim Moy)
    - Added block properties to the artwork system.  Text in the
      correct classes will add a property to the artwork rep.  So, in
      piglet you can say ADD N1019 :F0.5 "TOPLEVEL=TRUE" and place it
      anywhere in the artwork you want.  This also provides the
      capability of doing...
    - Conditional name promotion is supported now.  If you don't want
      name promotion to occur in a block you are going to submit for
      make_drc, add the property N_PROMOTE and set its value to FALSE.

12/15/88 PLA generation (Ed Weber)
    - Higher capacity blindfold program installed.

12/15/88 scip tools (Craig Heikes)
    - Added What strings
    - Modified AWSIM to fix reprep problem, memory usage, display problems,
      and added a simulate step command.

12/15/88 make_hcmp (Craig Heikes)
    - Added what strings
    - Fixed a bug with hcmp_filter

12/16/88 
    - Release 1.17a+27

    

From maj@hpesmaj Mon Dec 12 17:08 MST 1988
Received: from hpesmaj.HP.COM by hpfclr.HP.COM; Mon, 12 Dec 88 17:08:12 mst
Received: by hpesmaj.HP.COM; Mon, 12 Dec 88 17:07:26 mst
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8812130007.AA06897@hpesmaj.HP.COM>
Subject: BINV1 view
To: lab@hpesmaj
Date: Mon, 12 Dec 88 17:07:23 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: BINV1 view

  Yesterday (Sunday) at 12:30, and today at 2:30 somebody removed the
BINV1 view.  Please don't do this.  Generally the way this is done is by
retrieving a detail which includes BINV1 which has not been archived with
the :N1 option.  Remember these simple rules when editing and retrieving
archives:

  RULE #1: Don't edit and retrieve archives.  Remember that there is a
  nifty new command called CHA N :E =.  Use this--it's fun.

  RULE #2: There is no rule #2.

  RULE #3: If you decide you want to break rule number 1, before you
  edit--achive with the :N1 option!!!!  In this lab it important that we
  utilize 'safe-retrieval'.
--
		-Mike Jassowski

From jdy@hpesjdy Fri Dec  9 15:36 MST 1988
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Received: by hpesjdy.HP.COM; Fri, 9 Dec 88 15:38:39 mst
From: Jeff Yetter <jdy@hpesjdy>
Full-Name: Jeff Yetter
Message-Id: <8812092238.AA20472@hpesjdy.HP.COM>
Subject: Second try: pass-and circuit
To: lab@hpesjdy
Date: Fri, 9 Dec 88 15:38:33 MST
X-Mailer: Elm [version 1.7]
Status: RO


  To: ESL Lab
From: JDY
  Re: Pass-And circuit

     When using full complementary pass gates it is our practice to 
use an N-fet which is roughly twice as wide as the P-fet:

                                  |
                                __O___
                                ______
                    IN  _______|   1  |_____  OUT
                          |               |
                          |____    2   ___|
                               |______|
                               ________
                                  |

     This configuration usually yields the best performance.  When the
gates are turned on, the output rises quickly to Vdd -Vtn.  The final
rise to Vdd will take some extra time.  Vdd - Vtn is an acceptable 
1-level for most applications, but NOT for the gate of an N-type (only)
transfer gate.  This occured on the PMIN when a pass-and output was
used as a register set control line.  The circuit exhibits frequency
and Vdd sensitivity in excess of all other PMIN circuits.

     I suspect that for an optimum configuration under these 
circumstances the correct  P to N ratio should be closer to 2
(instead of 1/2).  At any rate, if you have used a pass-and (or
any pass gate) to qualify a set control, consider this advice and 
simulate carefully.



From chung-ching_yang%00@hp1900 Sat Dec 10 06:51 MST 1988
Received: from hpfcfa.HP.COM by hpfclr.HP.COM; Sat, 10 Dec 88 06:51:45 mst
Received: by hpfcfa.HP.COM; Sat, 10 Dec 88 06:16:24 mst
Full-Name: 
Date:         9 Dec 88 14:12 -0600
Subject:     PROGRAM PROPOSAL
Message-Id:  <36914703.0.0.0....@.HPDESK>
X-Hpdesk-Priority: 3
X-Hpdesk-System:  0
To: clinton_chao%00@hp1900, bob_dunlap%50@hp6400, mark_forsyth%01@hpc500,
        joe_fucetola@hpfcfa, denny_georg%01@hpc500, larry_hall%01@hpc500,
        larry_hanlon%00@hp1900, rob_horning@hpfcfa, dragan_ilic%10@hp6400,
        marcos_karnezos%00@hp1900, charlie_kohlhardt@hpfcfa,
        brian_leslie%00@hp1900, v_k_nagesh%00@hp1900, hanumant_patil%00@hp1900,
        ken_scholz%00@hp1900, paul_vanloan%50@hp6400, don_weiss@hpfcfa
From: chung-ching_yang%00@hp1900
Sender: chung-ching_yang%00@hp1900
Received: from hp4000 by hpfcfa; 10 Dec 88 5:13:46-MST (Sat)
Status: RO


     A  program  proposal for the System Engineering Department in the
     Electronics Packaging Laboratory (EPL) of  CT  R&D  is  attached.
     The   objective   of   this   program  is  to  develop  packaging
     design/tools to improve the  productivity  of  packaging  designs
     using  Tape  Automated  Bonding  (TAB)  and Pin Grid Array (PGA).
     This effort will be  extended  to  other  packaging  technologies
     (second,  third  and  forth level) in the future.  The outcome of
     this  program  will   privide   a   design   methodology.    This
     work-station  offers  guidelines  for  the  choice  of  packaging
     technologies, rules guided layout  designs,  design  verification
     and  design  optimization.   A  by-product  of this effort is the
     provision of measurement tools for  routine  characterization  of
     designed packages.

     This   is  a  three-phase  program.   The  attached  two  project
     proposals constitute phase 1 which will be commenced in 1989.

     The  intent  of  this  memo  is  to  inform our customers and CTG
     partners  and  solicit  their  critique  to  ensure  that   their
     interests and needs are better served by this program.

     Your  response  is  requested  by December 16, 1988.  Please feel
     free to call me at 1-857-8451 for clarifications  and  additional
     information.

.pa
                          PACKAGING DESIGN/TOOLS
                             PROGRAM PROPOSAL
                     ELECTRONICS PACKAGING LABORATORY


     The  mission  of  the System Engineering Department is to provide
     packaging design methodology and design tools for CTG and and its
     customers.    A  program  is  proposed  for  the  development  of
     packaging  design  tools   following   the   Packaging   Strategy
     recommendations established earlier this year.

     The  objective of this program is to improve electronic packaging
     design  productivity  through  the  implementation  of  a  design
     methodology   and  design  tools  which  are  integrated  into  a
     packaging  design  work  station.   The  program  aims  at  a  2X
     productivity  gain  in  two years.  This design methodology calls
     for a  technology  selection  guideline,  a  rule  driven  design
     process   for   selected   packaging   technologies,   a   design
     verification  process  using  model  simulation  and   a   design
     optimization  mechanism  using  the  packaging performance lookup
     table in conjunction with a back-annotation procedure.

     Productivity  improvement  in packaging design can be measured in
     the following way:

        1. Time  savings in technology selection with the provision of
           selection guideline.

        2. Cost  and  time  savings  in  design  cycle  time  achieved
           through:

           a. Reduction  in  revision  numbers of hardware fabrication
              using the design/optimization process  supplied  by  the
              design work station.

           b. More  effective  and  efficient  way  in  the  design of
              package using the design tools.

     The  strategy  is  to  work  with  CICD,  NID,  PRCD and leverage
     existing design, modeling and measurement tools.  New tools  will
     be  developed  based on needs only.  Initial focus will be placed
     on design tools which meet the current  packaging  design  needs,
     such as TAB and PGA.  To improve the effectiveness and efficiency
     of  packaging  design,  the  developed  design  tools   will   be
     integrated  into  a  design  work  station  formed  with a common
     skeleton of existing  CAD/CAE  tools  mutually  joined  together.
     Software compatibility will be specially emphasized.

     The  proposed  program  is structured in three phases each with a
     one year duration.  Completion  of  each  phase  will  deliver  a
     measurable  productivity improvement in packaging design.  The 2x
     productivity improvement will be aimed at the end of  the  second
     year.   Further  improvement  should  be  realizable  after phase
     three.  The following is a brief description of the  three  phase
     program:
.pa
     Phase  1: Develop  physical  models for the interconnect elements
               which constitute the building blocks for  the  selected
               packaging   technologies.   Then  construct  electrical
               models using  the  building  blocks  for  each  of  the
               selected      packaging     technologies.      Evaluate
               noise/performance for each packaging  technology  using
               an  analog  simulation  tool.  Validate all models with
               experiments  using  specially  designed  generic   test
               fixtures  and measurement approach.  A first cut system
               analysis will be  carried  out to compare TAB  and  PGA
               performance during this phase.

               Outcome  of  this effort will improve the effectiveness
               and efficiency in TAB/PGA package designs.  They  could
               also  potentially  help  reduce  the number of hardware
               iterations.  Consequently, a measurable improvement  in
               the package design cycle time should be realized.

     Phase  2: Define  performance  spaces  for the selected packaging
               technologies using  the  model  simulation  tools  with
               process  and  material limits as inputs.  Derive design
               rules  and  selection  guidelines  for   the   selected
               technologies.   Compile  performance  lookup  tables to
               enable back-annotation process for packaging designs.

               Outcome  of  this effort enables formulating guidelines
               for  packaging  technology  selection,   rules   driven
               packaging  designs  and  design  optimization using the
               back-annotation  capability.    Productivity   can   be
               measured  by  the time savings in technology selection,
               reduction in the number of design iterations  with  the
               design rules and back annotation process.

     Phase  3: Define  design work station skeleton. Develop data base
               and  library  structure  to  host  the  design   rules,
               performance   lookup  table,  component  and  packaging
               models.  Develop extraction tools to convert  packaging
               structures  into  electrical  representations  from CAD
               layout tools and to translate  the  design  rules  into
               rule  checking  format  for  CAD layout tools.  Develop
               linking software which is necessary  to  integrate  all
               required tools into a design work station.

               Outcome   of  this  phase  enables  development  of  an
               automated packaging design  process.   With  this,  the
               designer can do design, layout, verification and design
               optimization through his CAD layout  tool  (these  jobs
               are  traditionally  carried out by more than one person
               on   different   design   tools).    The   productivity
               improvement  can be measured by the reduction in design
               time and the availability of manpower for  doing  other
               tasks.

     Phase  1  through  3  will be completed by 11/89, 11/90 and 11/91
     respectively.  The following project proposals will address phase
     1  only, other project proposals will be submitted separately for
     phase 2 and 3 after the completion of each phase.

                                               _X_ 1ST AUTHORIZATION
                                               ___ REVISION #_______

                       HEWLETT-PACKARD LABORATORIES
                    PROJECT AUTHORIZATION & DATA SHEET
     _________________________________________________________________
     PROJECT IDENTIFICATION:          16 CHARACTER ABBREVIATED TITLE:

     19SCT110                         PKG MODL TAB/PGA

                        LAB: E.P.L.
                        DEPT: System Engineering
                              Department
                        LOCATION: 19-4820

      30 CHARACTER DESCRIPTIVE TITLE: PACKAGING MODEL PH1 TAB/PGA

      PROJECT MANAGER:  C. C. Yang     PROJECT LEADER:  Ravi Kaw
     _________________________________________________________________
     OBJECTIVES:
        Develop  generic  electrical  models for PGA and TAB to enable
     technology   selection,   packaging   design   optimization   and
     verification.  This includes:

     1.  Develop/acquire  physical models for the generic interconnect
         elements to be used as the building blocks for  TAB  and  PGA
         packaging models.
     2.  Develop/acquire  electrical  models for TAB and PGA to enable
         electrical simulation on an analog simulator.
     3.  Generate noise models for TAB and PGA.
     4.  Generate  a  first cut system analysis for TAB and PGA to aid
         technology selection.
     _________________________________________________________________
     CHECKPOINTS (Date and Description):

     1.  Existing electrical models for interconnect elements
         and package simulation of TAB/PGA surveyed/acquired.    2/89
     2.  Additional    necessary    electrical   models   for
         interconnect elements developed.                        4/89
     3.  Interconnect element models documented.                 6/89
     4.  TAB/PGA package simulation models available.            6/89
     5.  Noise/delay performance model established.              8/89
     6.  First cut system analysis for TAB/PGA completed         9/89
     7.  Package simulation models documented.                  10/89
     8.  TAB/PGA first cut system analysis documented.          11/89

                          ESTIMATED COMPLETION DATE:  11/89
     _________________________________________________________________
     STAFF: Bob Crawford(25%), Ravi Kaw(65%), Ken Lee(100%),
            Ralph Liu(100%), Frank perezalonso(25%), Jen-Te Wang(50%).

.pa
                      PACKAGING MODEL PHASE 1 TAB/PGA

     This  is  the  first  of  a  three-phase  program.   The  primary
     objective of this project is to develop the necessary  models  to
     aid  TAB  and  PGA  package  designs in that they can be used to
     verify as well as to optimize the package  design  without  using
     hardware.   This project is also intended to provide the critical
     inputs needed for the second phase of this program.

     The  model  building  process consists of three key steps:  First
     construct electrical models for the generic set  of  interconnect
     elements  which  constitute  TAB  and PGA packaging technologies.
     These  models  translate  the  physical   geometry,   dimensions,
     structures   and  material  properties  into  passive  electrical
     descriptions.   Then  use  the  interconnect  element  models  as
     building  blocks to construct the equivalent circuits for TAB and
     PGA.  The packaging models will be structured in generic forms so
     that they can be easily applied to any TAB/PGA designs.  The last
     step is to superimpose noise models  to  the  package  equivalent
     circuits to generate behavioral data.

     The  strategy  is  to  leverage  existing  modeling tools such as
     PACMAN, Greenfield (extraction tools), and analytical tools  from
     literature   to   generate   models  for  interconnect  elements.
     Modeling tools will be developed only on the  basis  of  absolute
     need.   Existing  TAB  and  PGA packaging models will be studied,
     they will be used whenever circumstances permit.

     The  system  behavior  of TAB and PGA will be analyzed with soft
     numbers.   Results  of  this  analysis  should  provide  a  rough
     comparison   between  the  two  technologies.   A  more  rigorous
     comparison and selection guidelines will be available at the  end
     of phase 2.





.PA
                                               _X_ 1ST AUTHORIZATION
                                               ___ REVISION #_______

                       HEWLETT-PACKARD LABORATORIES
                    PROJECT AUTHORIZATION & DATA SHEET
     _________________________________________________________________
     PROJECT IDENTIFICATION:          16 CHARACTER ABBREVIATED TITLE:

     19SCT111                         PKG CHARACTRIZTN

                        LAB: E.P.L.
                        DEPT: System Engineering
                              Department
                        LOCATION: 19-4820

      30 CHARACTER DESCRIPTIVE TITLE: PKG CHARACTERIZATION,TAB/PGA

      PROJECT MANAGER:  C. C. Yang     PROJECT LEADER: B. Crawford
     _________________________________________________________________
     OBJECTIVES:
     Design  test  fixtures and develop measurement techniques for the
     verification   of   packaging/interconnect    models.     Develop
     methodology  for  electrical  characterization  of  TAB  and  PGA
     packages.  This include:

     1.  Design,   fabricate   test   fixtures   to  simulate  TAB/PGA
         interconnect elements for interconnect model verification.
     2.  Design,  fabricate  test fixtures to verify the packaging and
         noise/performance models for TAB/PGA.
     3.  Develop  methodology  for  the electrical characterization of
         the performance metrics of TAB/PGA packages.
     4.  Develop an electrical measurement/data acquisition system for
         routine characterization of TAB/PGA packages.
     _________________________________________________________________
     CHECKPOINTS (Date and Description):

     1.  TAB/PGA interconnect element test fixtures available    5/89
     2.  TAB/PGA noise/performance test fixtures available       6/89
     3.  TAB/PGA interconnect element measurement techniques
         defined                                                 5/89
     4.  TAB/PGA interconnect element models verified            7/89
     5.  TAB/PGA noise measurement methodology defined           6/89
     6.  TAB/PGA package characterization methodology defined    7/89
     7.  TAB/PGA noise models verified                           8/89
     8.  TAB/PGA interconnect element measurement technique
         documented                                              8/89
     9.  TAB/PGA noise measurement technique documented          9/89
    10.  TAB/PGA package models verified.                        9/89
    11.  TAB/PGA characterization station completed             10/89
    12.  TAB/PGA characterization station documented            11/89

                         ESTIMATED COMPLETION DATE:  11/89
     _________________________________________________________________
     STAFF: Ron Bernard(50%), Bob Crawford(75%), Pete Dawson(50%),
            Ravi Kaw(15%), Frank Perezalonso(55%).
.PA
                     PACKAGE CHARACTERIZATION, TAB/PGA

     The  primary  objective  is to develop a verification methodology
     and process using test fixtures and  measurement  techniques  for
     TAB/PGA  interconnect  element  and packaging models.  The second
     objective is to develop  a  measurement/data  acquisition  system
     which  incorporates  these  measurement  techniques  for  routine
     characterizations of TAB/PGA packages.

     Test  fixtures  will  be  designed  and  fabricated to physically
     represent each of the interconnect elements  in  geometries  that
     were  represented  in  their  respective electrical models.  Test
     fixtures will be designed and  fabricated  for  TAB/PGA  packages
     where   only  the  generic  geometries  and  structures  will  be
     considered.   Measurement  techniques  will   be   developed   to
     characterize  the  electrical properties of interconnect elements
     and packaging structures.  Separate experiments will  be  devised
     to   investigate   noise   situations   under  various  operating
     conditions  in  the  packaging  structures.   Results  of   these
     measurements  are  to  be  used  to  validate the accuracy of the
     electrical models for interconnect elements, TAB/PGA packages and
     the noise behavior.

     Hardware   construction  is  a  time  consuming  process.   Model
     verification using test fixtures will be carried out only as spot
     checks.  Any  models which have been verified experimentally will
     not be repeated, the information will be  stored  into  our  data
     base.

     A  data acquisition/analysis system will be developed to automate
     the measurement techniques for TAB/PGA packages.   The  knowledge
     of  this  measurement  system will be made available to customers
     for their routine characterization of TAB/PGA packages.




From pjk@hpespjk Tue Dec  6 11:45 MST 1988
Received: from hpespjk.HP.COM by hpfclr.HP.COM; Tue, 6 Dec 88 11:45:03 mst
Received: by hpespjk.HP.COM; Tue, 6 Dec 88 11:45:32 mst
Date: Tue, 6 Dec 88 11:45:32 mst
From: Pat Knebel <pjk@hpespjk>
Full-Name: Pat Knebel
Message-Id: <8812061845.AA28867@hpespjk.HP.COM>
To: dmk@hpespjk, rjh@hpespjk
Subject: tools mounted
Status: RO

I copied tools to hpesrgd.  They are also mounted by hpesjes.

Pat

From htt@hpeshtt Mon Dec  5 17:10 MST 1988
Received: from hpeshtt.HP.COM by hpfclr.HP.COM; Mon, 5 Dec 88 17:10:49 mst
Received: by hpeshtt.HP.COM; Mon, 5 Dec 88 17:07:19 mst
From: Hoang Tran <htt@hpeshtt>
Full-Name: Hoang Tran
Message-Id: <8812060007.AA02550@hpeshtt.HP.COM>
Subject: Standard Cells Removed
To: lab@hpeshtt
Date: Mon, 5 Dec 88 17:07:11 MST
Cc: stm@hpeshtt
X-Mailer: Elm [version 1.7]
Status: RO



To : Standard Cell Users                        December 5, 1988

As we are approaching tape release, I'd like to clean up ctl to get some
more free space (that might be needed for the generation of mask data).
In doing so, following cells will be removed from the standard cell library 
database:

ARSET1Vl    BDRV1       BDRVL1      BJUNK86     BOR12       BND3_b1	    
BND3_t1     BOAI21      BOCHK1      CTLAT       FBLUF1      FBLUF2      
FFLOW1      FGRAPH1     FGRAPH2     FGRAPH3     FPAL1       FREDF1      
FREDF2      FTEST       FTEST1      FTEST1F     FTEST2      HVDD1       
HTTREG1     LJSCON1     LJSCON2     LJSPAD1     MDRV1       MDRVL1
MMX31F      MS1         MS2         MS3         
LGND0       NP5         NPAD31      NPAD32      PBCHK1      PLACOR1     
SCLD000     SCLD201     SCLD202     SCLD301     SCLD302     SCLD303
SCLD401     SCLD402     SCLD403     SCLD404     SCLD501     SCLD502
SCLD503     SCLD504     SCLD505     SCLD601     SCLD602     SCLD603
SCLD604     SCLD605     SCLD606     SCLD701     SCLD702     SCLD703
SCLD704     SCLD705     SCLD706     SCLD707     SCLD801     SCLD802
SCLD803     SCLD804     SCLD805     SCLD806     SCLD807     SCLD808
SCLD901     SCLD902     SCLD903     SCLD904     SCLD905     SCLD906
SCLD907     SCLD908     SCLD909     SCLD990     SCLD990_b1  SCLD990_l1
SCLD990_r1  SCLD990_t1  SCLD999     SCLDB1      SCLDL1      SCLDR1
SCLDT1      SCLD_b1     SCLD_l1     SCLD_r1     SCLD_t1     SCAN901     
SNAND2_b1   SNAND2_t1   SOAI21      TEST.pad1   TEST.pad2   YVIA1

If you are using any of these cells (I hope not..!), or for any reason, 
you want any of them not to be removed, please let me know by Thursday 
December 8, 1988.

htt
x3334


P.S.  There will be a "backup" copy of all removed cells for those who 
      can not make up their mind now (prices are seasonal).


From rwm@hpesrwm Mon Dec  5 16:28 MST 1988
Received: from hpesrwm.HP.COM by hpfclr.HP.COM; Mon, 5 Dec 88 16:28:52 mst
Received: by hpesrwm.HP.COM; Mon, 5 Dec 88 16:25:22 mst
From: Russ Mason <rwm@hpesrwm>
Full-Name: Russ Mason
Message-Id: <8812052325.AA01713@hpesrwm.HP.COM>
Subject: core file in users/vectors on rjh
To: rjh@hpesrwm
Date: Mon, 5 Dec 88 16:25:17 MST
X-Mailer: Elm [version 1.7]
Status: RO

Rob

Did you know that you have a 2.3Mbyte core file in /users/vectors on
your machine?

Russ

From trh@hpestrh Wed Nov 30 20:38 MST 1988
Received: from hpestrh.HP.COM by hpfclr.HP.COM; Wed, 30 Nov 88 20:38:09 mst
Received: by hpestrh.HP.COM; Wed, 30 Nov 88 20:33:34 mst
From: Tom Hotchkiss <trh@hpestrh>
Full-Name: Tom Hotchkiss
Message-Id: <8812010333.AA21663@hpestrh.HP.COM>
Subject: New Timing Budget Utility
To: timing@hpestrh
Date: Wed, 30 Nov 88 20:33:29 MST
X-Mailer: Elm [version 1.7]
Status: RO


To: Anyone who is responsible for timing budgets

From: Tom Hotchkiss

Date: 11/30/88

I have written a utility that will help you find out how much margin there
is associated with any particular budget item in the PCX timing budget
data base.  You simply call the utility with the name of the budget item
of concern, and it will search the data base and produce a brief report
containing:

   - The name of the budget item
   - All lines from the budget_defs file where the budget is defined
   - A list of the top ten limiting frequency paths that contain the
     budget item.

This utility should prove useful to anyone who is trying to meet speed
specs.  (If you aren't responsible for budget items in the system timing
budget data base, then read no further).  You can run the utility to
determine whether or not there is margin in your budget.  Until now,
designers have been coming to me to find out if there is margin in their
budgets.  Now, you can just use this utility to find out.

NOTE: There is one major potential problem with distributing this utility.
      Two people can run the utility simultaneously on two different budget
      items.  If the two budget items are used in the same timing path, then
      each designer may try and use the full margin from that path, resulting
      in a path which does not meet the goal.

      In light of this, I would like to recommend the following guidelines
      for using the utility:

      1.  Once you run the utility, if you need any of the available margin,
          come let me know ASAP, so that I can update your budget item and
          remove the margin from the data base.

      2.  Don't use more margin than you need; i.e. let me know what speed
          your circuit actually runs at.  Similarly, if you design a circuit
          that runs faster than the current spec in the data base, let me
          know so that I can adjust the budget down to its actual speed.
          This keeps the maximum margin in the data base for other designers
          to take advantage of.  It doesn't make sense for one designer to
          sweat bullets trying to squeak the last .5ns out of a circuit when
          some other circuit in the path exceeds its budget by 2ns.

       3. This implies that the timing budget data base will change
          frequently.  So, you should re-check for margin frequently.
          (i.e. margin that exists in a budget item today, might not
           be there tomorrow.)


Now for the gory details-

The script is contained on my machine in "/users/trh/bin/margin".  You can
copy this script over to your own machine or execute it over the net, but
don't forget, executing commands across the net eventually makes your machine
bomb.

Once you have copied the script, to run it just type:

   margin budget_item

where budget_item is the name of the item you want to test.  The script prints
a report to the standard output.  The script takes a minute or longer to run,
depending on the total number of paths containing the budget item, so you
may want to redirect the output to a file.  Also, there is a "head -10"
command at the end of the script that causes just the top 10 limiting paths
to be output.  You can go into the script and change this if you want.

One final note of caution, this thing hasn't been extensively QA'ed, and has
little or no error checking.  So use it at your own risk and let me know if
you have any problems.

Thanks,

Tom "the timing guy" Hotchkiss

From wdk@hpeswdk Fri Dec  2 09:40 MST 1988
Received: from hpeswdk.HP.COM by hpfclr.HP.COM; Fri, 2 Dec 88 09:40:38 mst
Received: by hpeswdk.HP.COM; Fri, 2 Dec 88 09:36:28 mst
From: Wayne Kever <wdk@hpeswdk>
Full-Name: Wayne Kever
Message-Id: <8812021636.AA19784@hpeswdk.HP.COM>
Subject: Getting the right BDL to SPICE
To: lab@hpeswdk
Date: Fri, 2 Dec 88 9:36:25 MST
Cc: rtn@hpfirtn
X-Mailer: Elm [version 1.7]
Status: RO


I found out yesterday that make_spice does not do any date checking.  If you
specify mix mode and it finds a hier_cap.max, that BDL will be selected
without comment, even if a DRC has been done since the last cap extract.  This
is not normally a problem, but it could be if someone forgot to re-run cap
extract after changing a cell`s artwork.  

Rich Nash has agreed to change make_spice to echo a warning message to the 
spice/list file if the bdl.out is newer than the hier_cap.max.  The cap extract
BDL will still be used.  The moral of this story is to delete any cap extract
BDL that is out of date, and to check the spice/list file for warnings after
formatting, particularly for blocks which have leveraged children.

From maj@hpesmaj Fri Dec  2 13:50 MST 1988
Received: from hpesmaj.HP.COM by hpfclr.HP.COM; Fri, 2 Dec 88 13:50:15 mst
Received: by hpesmaj.HP.COM; Fri, 2 Dec 88 13:49:14 mst
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8812022049.AA14576@hpesmaj.HP.COM>
Subject: update monday
To: lab@hpesmaj
Date: Fri, 2 Dec 88 13:49:12 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: Tool update monday

  Yes, it's that time of the week again...Here's what they have planned
for us this week (looks like some pretty boring stuff this week):
--
		-Mike Jassowski

11/21/88 start (Paul Nuber)
    - Added X11 piglet artwork.

11/21/88 art.cbm (Paul Nuber)
    - Added message before compact command to see how long it takes.
    - Improved messages for fast drc.
    - Added workaround for NFS-piglet problem.

11/21/88 bdltodf (Steve Herbener)
    - Fixed problem where bdltodf would flag an @ in the BDL description
      as a syntax error in a place where it was actually legal.

11/22/88 cmos34 ART.MAC (Paul Nuber)
    - Fixed piglet POST macro.

11/25/88 bippy (Alexander Elkins)
    - Fixed the bmdb traversal procedure to check only the hierarchy required
      for the specific rep named by the -r option when it is given.

11/28/88 cp_block, mv_block (Rich Nash for Mark Hammer)
    - Fixed problem that occurred when the number of parameters were greater
      than ten.

11/28/88 x11ready, what_win (Paul Nuber)
    - added X11 window detection

11/28/88 make_cpf (Rich Nash)
    - modified to include diode models for cmos34. Previously diode models
      were only included for cmos26 users. This required changes to the spice
      model files. A key word for cpf was added as a comment to the files
      NOM, SLOW, FAST, LTRAN, RTRAN, MINPOW, MAXPOW for both 26 & 34.

11/29/88 cmos34 & cmos40 art config (Paul Nuber & John Morgan)
    - minor updates to artrc, art_sets, ART.PRO

11/29/88 clear_block (Rich Nash)
    - added rep hcmp which is created by make_hcmp

11/30/88 hier_status (Paul Nuber)
    - missing bm.db would cause core-dump messages to be printed

11/30/88 make_drc (Jim Moy)
    - Fix to trantor so some names which weren't getting promoted
      (and should have been) are now promoted correctly.

12/1/88 PLA generation (Ed Weber)
    - Added script $CBROOT/hbdcb/bin/tran2hbd to convert trantor.db's
      to hbd files.  Can be used to recover from some plagen aborts.
    - plagen terminus script modified to use tran2hbd.
    - -no_hbd option added to plagen script for use when trantor
      editor is being used. (suppresses call to tran2hbd)

12/1/88 
    - Release 1.17a+24


From maj@hpesmaj Tue Nov 29 17:24 MST 1988
Received: from hpesmaj.HP.COM by hpfclr.HP.COM; Tue, 29 Nov 88 17:24:28 mst
Received: by hpesmaj.HP.COM; Tue, 29 Nov 88 17:13:11 mst
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8811300013.AA07593@hpesmaj.HP.COM>
Subject: unix security hole
To: lab@hpesmaj, willy@hpesmaj, paulf@hpesmaj, annika@hpesmaj
Date: Tue, 29 Nov 88 17:13:08 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: Unix security hole

   It has just been brought to our attention that there is a 'well known'
security hole in HP-UX.  Any shell scripts which are setuid and begin with
the line:

#!/bin/sh (and presumably *sh (csh, ksh, rsh, etc.))

and are executable by the world (or an unsecure group), are security holes.

ANY user logged into a machine with such a program can EASILY become root
with only a few commands.

There are two reasons I am bringing this to your attention:

  1) The 'step-by-step' method for utilizing this method has just been
distributed on an hp wide notes group (includes the field).

  2) Such a script was DISTRIBUTED with HP-UX 6.2.

  I have taken the liberty of removing the world execute permission from
the script in question (vhe_u_mnt: a script which allows joe_user to mount
directories listed in a cross-reference file).  Unfortunatley, the nature
of the program is such that it becomes useless with world permissions
removed.  However, I don't believe that this script is used in our lab (if
anyone knows otherwise, please let me know).

  If there is anyone in our lab writing/distributing setuid scripts, please
make sure the first line does NOT contain a:

#!/bin/<some shell>

or remove the execute permission for world (might as well remove the setuid
flag).  If you have updated to 6.2, or will in the future, and you don't
have a janitor account, to secure your system execute the following
commands:

chmod 4510 /etc/newconfig/vhe_u_mnt
chmod 4510 /usr/etc/vhe/vhe_u_mnt

Remember: The data you save may be your own.
--
		-Mike Jassowski

From maj@hpesmaj Fri Nov 18 09:40 MST 1988
Received: from hpesmaj.HP.COM by hpfclr.HP.COM; Fri, 18 Nov 88 09:40:23 mst
Received: by hpesmaj.HP.COM; Fri, 18 Nov 88 09:39:18 mst
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8811181639.AA07472@hpesmaj.HP.COM>
Subject: update done/monday's update
To: lab@hpesmaj, willy@hpesmaj, paulf@hpesmaj, annika@hpesmaj
Date: Fri, 18 Nov 88 9:39:13 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: Update finished, plus info on monday's scheduled update.

  The non-scheduled update for this morning is finished.  Info on Monday's
update follows.  Highlights include a notice about re cap-extracting blocks
with PAD layers, and a new program called make_hcmp--a program which
bdl-compares Standard cell blocks.
--
		-Mike Jassowski

11/14/88
    - Updated cap/sym/trantor.db under all the primitives directories.
      Since this is a dummy trantor db and none of the programs depend
      on it, it shouldn't affect anyone but those who are typing trantor
      on the command line.

11/16/88
    - New capacitance extract scripts now perform continuity extraction
      on pad layers.  This fixes a problem where a block with a pad layer
      had a port which didn't show up in the parent as a junction.

         *******************************************************
          BLOCKS CONTAINING PAD LAYERS MUST BE RE-CAP-EXTRACTED
         *******************************************************

      This does not mean that they need to re-verified since only the
      capacitance data is invalidated, and only if there are pad
      layers in the block.  The following commands will clear only the
      cap-extracted data, leaving the drc'd, verified data intact, and
      re-run the capacitance extract.

             clear_block -d -f -r cap <block>
             make_cap <block>

      The updated scripts are cap_setvars, cap_seteval, and cap_layers.

11/17/88 FUNGEN (Harlan Talley)
    - Added schtoalias function
    - Changed menu to accept lower case letters for 'Q', 'T', and 'D'

11/17/88 CMCPAL1 palette device in cmos26,34 schematic prims (Steve Herbener)
    - Deleted bad reference in the bm.db files to the device 'ZDT0'.
      ZDT0 no longer exists, but the references to it in the bm.db files
      were not cleaned up when ZDT0 was deleted. This fix should have
      absolutely no effect on any cbmake command (eg, makemod).

11/17/88 make_hcmp (Rich Nash, Craig Heikes)
    - Runs NID's hcmp program.
    - Can be used to compare all blocks including harp generated
      blocks.
    - See man page for additional details.

11/17/88 PLA Generation (terminus/trio, Ed Weber)
    - Enhanced bit line capacitance report.
    - Bug in stretched array support circuit layout fixed.

11/17/88 scformat (cah)
    - Fixed a bug with parsing california bdl.

11/18/88 startguide (Rich Nash)
    - Added script to start guide without windows.

11/18/88 
    - Release 1.17a+23


From bja@hpesbja Fri Nov 18 10:02 MST 1988
Received: from hpesbja.HP.COM by hpfclr.HP.COM; Fri, 18 Nov 88 10:02:39 mst
Received: by hpesbja.HP.COM; Fri, 18 Nov 88 10:07:07 mst
From: Barry Arnold <bja@hpesbja>
Full-Name: Barry Arnold
Message-Id: <8811181707.AA00792@hpesbja.HP.COM>
Subject: Lets Make a DEALY!
To: cmux_group@hpesbja
Date: Fri, 18 Nov 88 10:07:04 MST
X-Mailer: Elm [version 1.7]
Status: RO



	Hey Fellow Cmuxers,

	The  DEALYs are here.  What this  means is that you have to stop
	complaining  about when  they will be done and put them in  your
	receiver block.  ( so there!!!  )

	For the uninitiated, the DEALYs are the receiver control de-skew
	elements  which must be added to all of the  reciever  blocks on
	the  cmux.  So if you are not  fortunate  enough to be  involved
	with any  receiver  blocks, you  probably  could care less about
	this.

	In  order  to help  the  rest of you  figure  out how to use the
	DEALYs, the manufacturer has thoughtfully included several items
	which may be of interest.  They are:

	1) Data Sheets:  these are in the DEALY directories and give all
		of the design critical specs of the DEALY twins.  By the
		way, the  DEALYS are at  ".../disk2/release/DEALY1"  and
		".../disk2/release/DEALY2".   READ IT.

	2) An Example:   how lucky  can  you  get,  just take a look  at
		".../disk3/release/RDRAS1" and you can see the DEALYs in
		action.  This is a ram reciever block.  The signal names
		may  change for your  block but it does  show the  basic
		idea of how the DEALYs are intended to be used.

	3) Guide Lines:  this  is the  data  which PRB  has  distributed
		showing all receiver  blocks along with their associated
		DEALYs. This is very useful for determining what signals
		connect to your DEALYs.   Please note that this does not
		show connections to the PON  signal and is  represents a
		logical not  physicaly  depiction of the  DEALYs in  use.
		Just   remember  the  little  rule   provided   by   the
		manufacturer: "Never a DEALY2 without a DEALY1".

	Good Luck and Happy DEALYing,

	Barry

From ren@hpfclhe Mon Nov 21 09:40 MST 1988
Received: from hpfclhe.HP.COM by hpfclr.HP.COM; Mon, 21 Nov 88 09:40:54 mst
Received: by hpfclhe.HP.COM; Mon, 21 Nov 88 09:38:35 mst
From: Bob Naas <ren@hpfclhe>
Full-Name: Bob Naas
Message-Id: <8811211638.AA06076@hpfclhe.HP.COM>
Subject: Top Level CMUX Connections
To: rjh@hpfclhe
Date: Mon, 21 Nov 88 9:38:29 MST
X-Mailer: Elm [version 1.7]
Status: RO


 Rob,

 There are a few top level connections that will have to be made in
 the CMUX model after the latest DPC1 block update.  There are several
 CLDs that come out of the DPC1 Core that feed back in as inputs.
 These lines will be ported all the way to the top level to allow
 the channel router to handle them.  Here are the connection declarations
 that will have to be made at the top level:
 
  SPREV_WGOH[0:4] = SPREV_WGH[0:4]
  SBHIT_CMPOH = SBHIT_CMPH
  SCDI_DCNTLOH = SCDI_DCNTLH
  SCDI_DR0OH = SCDI_DR0H
  LATCH_PEOH = LATCH_PEH

From rwm@hpesrwm Mon Nov 21 10:06 MST 1988
Received: from hpesrwm.HP.COM by hpfclr.HP.COM; Mon, 21 Nov 88 10:06:53 mst
Received: by hpesrwm.HP.COM; Mon, 21 Nov 88 10:03:26 mst
From: Russ Mason <rwm@hpesrwm>
Full-Name: Russ Mason
Message-Id: <8811211703.AA01304@hpesrwm.HP.COM>
Subject: DEALYs
To: cmux_group@hpesrwm
Date: Mon, 21 Nov 88 10:03:23 MST
X-Mailer: Elm [version 1.7]
Status: RO


Since the DEALYs need to be in the schematics before I can perform parallel
loads and dumps of the receiver scan latches, please let me know when the 
DEALYs have been included in your schematics.  Remember that all levels of 
hierarchy must be updated--including the view of your top level block.  
 
I expect that the DEALYs will be completed in the next day or so.  If this
is not consistent with your plans, please let me know.


Russ

From maj@hpesmaj Mon Nov 14 08:58 MST 1988
Received: from hpesmaj.HP.COM by hpfclr.HP.COM; Mon, 14 Nov 88 08:58:20 mst
Received: by hpesmaj.HP.COM; Mon, 14 Nov 88 08:50:58 mst
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8811141550.AA08679@hpesmaj.HP.COM>
Subject: tool installation done
To: lab@hpesmaj, willy@hpesmaj, paulf@hpesmaj, annika@hpesmaj
Date: Mon, 14 Nov 88 8:50:56 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: Update finished

  Yes, it's Monday morning, and yet another update is done.  Not too much
new, just a few bug fixes (see below).

  Note to HARP users:  The mold fix was included with this release.  To
take advantage of this fix you must add the line:

   weight_mult=1

to your harp.init file *outside* of the option list.  Please note that
this may have several effects on your design.  If the same net at two
levels of heirarchy are given weights, the total weight on the net will
be the product of all the individual weights.  Also, since weights will
not be truncated to 1-9, there may be some designs out there with weights
which are too large.  (You will get an integer overflow in camel if your
wieghts are too high.)  This is entirely a function of each particular
design, so I cannot recommend a standard 'maximum weight'.  However,
reducing the value of your local nets parameter with:

   local_nets="-l=<value>"

where <value> is an integer (the default is 360), can help to allow
larger weights.
--
		-Mike Jassowski


11/7/88 arc2mebes splot chip_release (Paul Nuber)
    - blank lines and man pages removed

11/7/88 clear_block (Paul Nuber)
    - clear_block -b removes empty directories so bippy can clean up bm.db

11/7/88 waiver (Paul Nuber)
    - Cleans up /tmp files better when it is through.

11/8/88 pigin (Alexander Elkins for Fu Dain/Ed Lock)
    - Changed limit on max reference crosses that can be stretched from 8 to 32.

11/9/88 terminus PLA generation (Ed Weber)
    - dor_bus_dev blockpiece now included in river routes.  This fixes the
      problem of the river routes hiding a GND port to the core block (cmos26).

11/9/88 mold (Rich Nash, Mike Jassowski)
    - modified to output WEIGHTS as integers

11/10/88 make_cap (Jim Moy, Rich Nash)
    - New trantor fixes problem in merging routines which would cause
      a premature abort during capacitance extraction.

11/10/88 cpf_spice (Rich Nash)
    - Fix for inclusion of multiple .CONFIG statements in cpf spice
      files

11/10/88 scformat (Craig Heikes)
    - Fixed a bug when parsing California BDL's (the NET: bug)

11/10/88 h3run.cb (Craig Heikes For Mike Jassowski)
    - new version

11/11/88 sch_to_art (Harlan Talley)
    - Fixed bug in FUNGEN sch_to_art 'extend' option so it extends left properly

11/11/88
    - Release 1.17a+21


ninstall: Installing from hpzit...
ninstall: *** hybrid-rev ***
ninstall: Installed /tmp/hbdCHANGES
ninstall: rm /tmp/hbdCHANGES


From maj@hpesmaj Mon Nov  7 08:58 MST 1988
Received: from hpesmaj.HP.COM by hpfclr.HP.COM; Mon, 7 Nov 88 08:58:22 mst
Received: by hpesmaj.HP.COM; Mon, 7 Nov 88 08:53:23 mst
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8811071553.AA18193@hpesmaj.HP.COM>
Subject: Update finished
To: lab@hpesmaj, willy@hpesmaj, paulf@hpesmaj, annika@hpesmaj
Date: Mon, 7 Nov 88 8:53:20 MST
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: Update finished

  The tool update is finished.  BTW, here is the list of updated programs:
--
		-Mike Jassowski

10/31/88 clear_block (Paul Nuber)
    - improved check for trantor-is-source
    - removes empty directories

10/31/88 make_drc make_cap make_mebes make_mask (Paul Nuber)
    - unset BLOCKPATH before running bippy, so inaccessible paths in BLOCKPATH
	don't stop make_drc.

10/31/88 ART.MAC ART.PRO (Paul Nuber)
    - additional layers defined

11/1/88 simset script in GUIDE customization (Steve Herbener)
    - Took out line which clears out EXPREPLIST. This was done so that the
      user can set EXPREPLIST in their ~/.guiderc file and EXPREPLIST won't
      get cleared out when they select a simulator. If you don't set EXPREPLIST
      explicitly, the makemod command will use a default as it did before this
      change.

11/2/88 Qdrc Qcap Qmebes Qmask (Paul Nuber)
    - removed absolute path to Qstatus.  Added Qmebes.

11/2/88 Qawsim Qbest (Paul Nuber)
    - removed absolute path to Qstatus

11/2/88 Harlan Talley (Fungen)
    - added directories $CBROOT/cmos26/fungen_tables and
      $CBROOT/cmos34/fungen_tables for generic fungen
      configurations.  Placed the sch_to_art configuration
      in those directories.

      ****************************************************
      Your FUNGEN_TABLEPATH should now include:
      $CBROOT/$ICPROCESS/fungen_tables
      ****************************************************

11/2/88 make_spice (Rich Nash)
    - First line in file was missing #!/bin/ksh. This caused
      cd failure when running jobs locally.

11/2/88 pig_dev_list (Rich Nash)
    - Removed limit for block names of more than eight
      characters.

11/2/88 cmos26/etc/err.map (Paul Nuber)
    - Added new error classes.

11/2/88 rmsig (Steve Herbener)
    - Fixed bug where rmsig would core dump when the -p option (strip
      uninteresting pad ports) was used during the processing of a harp deck.

11/3/88 PLA Generation (terminus, Ed Weber)
    - `nolabel' port tag operation by trio changed to only affect
       artwork, not the bdl.
    - Trio report file summation of `other signal' properties now
      broken down by I/O driver block.

11/3/88 cmos40 (John Morgan, Randy Fiscus)
    - cmos40 directories etc, piglet and scripts released.

11/3/88 rmcub (Dave Pinsky)
    - Added -v flag for outputting info about blocks/files still left in
      cubbyhole directories such that the cubbyhold directory is unable
      to be removed. 
    - Also added error detection for blocks that were 
      to be removed that did not get removed (rm -rf failed).  
      This report does not depend on the -v flag.

11/3/88 setcub func.setcub (Dave Pinsky)
    - Script to report to users that setcub is a function that must
      be define by executing ". $CBROOT/bin/func.setcub".

11/3/88 make_drc (Jim Moy)
    - New trantor eliminates the core-dump problem during "Circuit Extract."
      Problem was a merging routine missing from the most recent PCO'd
      1.17 libraries.

11/3/88 scip programs (Craig Heikes)
    - All programs modified to fix shared memory problems between windows.
    - scspicep: Fixed Distance measuring symbols, fixed reading of incomplete
      raw data files. 
    - scawsim: Added $PRINT_QUEUE for queue printing, Changed undriven node
      assertions, Fixed the auto creation of control and signals files, Fixed
      the reporting of gate only nodes.
    - scformat: Fixed the auto creation of SPICE control files.

11/4/88
    - Release 1.17a+20


From maj@hpesmaj Fri Oct 28 10:44 MDT 1988
Received: from hpesmaj.HP.COM by hpfclr.HP.COM; Fri, 28 Oct 88 10:44:43 mdt
Received: by hpesmaj.HP.COM; Fri, 28 Oct 88 10:42:34 mdt
From: Mike Jassowski <maj@hpesmaj>
Full-Name: Mike Jassowski
Message-Id: <8810281642.AA18675@hpesmaj.HP.COM>
Subject: Another monday morning update
To: lab@hpesmaj, willy@hpesmaj, paulf@hpesmaj, annika@hpesmaj
Date: Fri, 28 Oct 88 10:42:30 MDT
X-Organization:  Hewlett-Packard, Engineering Systems Laboratory
X-Sub-Entity:  Fort Collins Facility
X-Mailing-Address:  Mail Stop 55, Building 2-Upper
X-Hp-Telnet: 1-229-2574
X-Usenet: hplabs!hpfcla!hpstob!maj
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

To: Lab
From: Mike Jassowski
Re: Another Monday morning update.

  There will be another Monday morning tool update.  Following is a list of
modifications to the tools:
--
		-Mike Jassowski

10/25/88 harpcap2bdl (Tom Walley)
    - Part of the new harp -> spice, cpf path.
    - Harpcap2bdl creates harp_cmos26/harpcap_bdl which is a new target in
      spice.cbm.  Harpcap_bdl is harp_bdl with all the capacitors from
      <block>.cap added.
    - Initial revision

10/25/88 harp_cap (Tom Walley)
    - Part of the new harp -> spice, cpf path.
    - Initial revision

10/25/88 h3run.cb (Tom Walley)
    - Part of the new harp -> spice, cpf path.
    - Added a call to harpcap2bdl.

10/25/88 spice.cbm (Tom Walley)
    - Part of the new harp -> spice, cpf path.
    - Changed the mixed spice deck generation from art& sch
      to art & harp & sch in that order.

10/25/88 make_cpf (Tom Walley)
    - Part of the new harp -> spice, cpf path.
    - Removed the code that implemented the '-h' option.  Make_cpf no longer
      adds harp capacitances to a finished spice deck.

10/25/88 PLA generation (Ed Weber)
    - Added experimental BLIF output command blifo to terminus.
    - Removed placebo command from terminus.
    - quikpla program deleted.
    - Added array support cell labeling block pieces to trio (terminus).

10/25/88 h3run.cb (Mike Jassowski)
    - removed hard coded path for harpin

10/25/88 rmsig (Mike Jassowski)
    - fixed nonconnected signal bug

10/25/88 bippy (Alexander Elkins)
    - Added support for NFS/DUX/SLINK paths, now requires rsemd to run.
    - Changed to write 2.0 bmdb format.
    - Various speed-up improvements.
    - Drasticly reduced virtual memory requirements.
    - Removed idsig (-i) option.
    - Rebuild option (-b) now deletes rep's from the bmdb which no longer exist
        under the block directory.
    - Added some syntax checking to the command line option parsing.
    - Updated the man page.

10/25/88 sch_to_fgn (Harlan Talley)
    - Fixed malloc bug

10/25/88 cp_block_files (TDS Sudhakar)
    - Fixed a bug with return codes.  Even though there were some errors in
      copying, this utility returned a zero exit code and mv_block thought
      that copy is successful and removed the source block thus leading to
      data loss.

10/26/88 mv_block, rm_block (Rich Nash)
    - In some cases did not set the block management pointers correctly.
    - Change some error messages

10/26/88 make_awsim, make_best, make_spice (Steve Herbener)
    - Changed messages that used $0 to use a variable that was set to
      `basename $0` so that just the script name is echoed instead of the
      whole path the user typed in.

10/26/88 make_cap (Jim Moy)
    - ** Trantor no longer core-dumps! **
    - Fix bug in trantor.db connectivity representation which is needed
      by ERC.  This does not affect capacitance values for logical signals.
    - DTC speedup of ccap command by 6x has been included for several
      releases, but never got into this log file.  Here it is.  A few other
      algorithm improvements remain to be made, but this was the first order
      improvement.

10/27/88 hbd_filter.src, hbd_src_filter (TDS Sudhakar, Rich Nash)
    - Some patterns like 'art.*/piglet\.db' are ambiguous and match files like
      '/net/hpfidjn/artwork1/......../encap_cmos26/piglet.db'. Now the above
      pattern is replaced by 'art[^/]*/piglet\.db' which truely matches
      piglet.db only in artwork reps.

10/27/88 cmos34/guide.cbm (Rich Nash)
    - path to a command newer was wrong

10/27/88 conv_bmfiles (Rich Nash)
    - Fix to handle old format master files which unfortunately still
      haunt us.

10/27/88 makearc (Steve Herbener)
    - An old version of makearc accidentally got into the HARP release. This 
      change is merely replacing the old makearc back with the latest one
      which has been working okay in the system since June 88.

10/27/88 terminus (Harlan Talley)
    - fixed malloc bug which only occurs with very long paths when
      creating madl

10/27/88 sch_to_fgn (Harlan Talley)
    - added ability to use with folded schematics

10/27/88 cpdesign cbhupdate (Rich Nash)
    - changed to use new block management format
    - removed references to bdl rep

10/27/88 PLA Generation (Ed Weber)
    - plagen script now creates test.par file in modgen directory.

10/27/88 SCIP programs (Craig Heikes)
    - modified scformat to output a new format of AWSIM alias file which is 
      sorted.
    - modified scawsim to work with either format of alias file and fixed
      a bug with post processing.

10/27/88 cmos34 art.map, err.map and ART.MAC (John Morgan)
    - corrected guard ring layers in art.map.
    - added cap implant width and space error layers to err.map and ART.MAC.

10/28/88
    - Release 1.17a+19

From sru@hpessru Mon Oct 24 15:03 MDT 1988
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Date: Mon, 24 Oct 88 15:02:12 mdt
From: Steve Undy <sru@hpessru>
Full-Name: Steve Undy
Message-Id: <8810242102.AA09179@hpessru.HP.COM>
To: mal@hpessru, rjh@hpessru
Subject: Awsim vectors
Status: RO


Help!

My file system is full due to a large number of large awsim vectors in
my /tmp directory.  If you want these vectors please move them to one
of your machines, otherwise I will remove them altogether.

Thanks

Steve

From hargis Mon Oct 24 16:13 MDT 1988
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Date: Mon, 24 Oct 88 16:07:47 mdt
From: Jeff Hargis <hargis>
Full-Name: Jeff Hargis
Message-Id: <8810242207.AA09635@hpfclr.HP.COM>
To: hargis@hpfclr, jim@hpfclr, kehoe@hpfcla, leith@hpfclr, rand-b@hpfcla,
        rjl@hpfcla, rob@hpfcla, russ-s@hpfclr, sh@hpfcla, toms@hpfclr
Subject: Hoops
Status: RO



    Foxtrotters,

    The HP basketball league organizational meeting and team sign-ups
    will be held Tuesday, Oct. 25 at 4 pm in 3LC5.  I will attend on
    our teams behalf, anyone else who is interested can also attend.

    I am planning on signing us up for the "Competitive League".  My
    guess is we'll be fighting to break .500 in this league, perhaps 
    better if our big guys show up consistently.  If we returned
    to the rec league, we'd probably win every game by about
    25 pts, much like last year.  Though it would be fun to extend
    our winning streak and defend our championship, I'm afriad that
    some of the rec teams may grow tired of losing 78-14 and we'd
    be looked upon as bullies.  If anyone objects to our moving up
    to the competitive league, please let me know before Tuesday's
    meeting.

    Our next practice is Tuesday, Oct. 25, at 6:30 pm in the Timnath
    Arena Auditorium.  The competitive league is going to be tough,
    so please show up!           



From wnw@hpeswnw Mon Sep 26 15:23 MDT 1988
Received: from hpeswnw.HP.COM by hpfclr.HP.COM; Mon, 26 Sep 88 15:23:47 mdt
Received: by hpeswnw.HP.COM; Mon, 26 Sep 88 15:13:15 mtd
From: Bill Weiner <wnw@hpeswnw>
Full-Name: Bill Weiner
Message-Id: <8809262113.AA11448@hpeswnw.HP.COM>
Subject: man pages
To: lab@hpeswnw (entry systen lab)
Date: Mon, 26 Sep 88 15:13:09 MTD
X-Mailer: Elm [version 1.7]
Status: RO

Hey Lab,

   All hbdcb man pages on lbm can now be accessed through rman.  Just type
'rman trantor' if you want the man page for trantor.  There are still a 
few things you should know about the man page service.

   Sometimes the hbdcb man page you are looking for is named the same as a 
hp-ux command and the unix man page is found first.  One command that has this 
problem is the plapen command asa.  In this case you can force the finding 
of the hbdcb man page by typing 'rman tools,asa'.  This will find the hbdcb
man page and not the unix man page for asa.  Note there can NOT be any
spaces next to the comma.  

   Due to problems in the way the hbdcb man pages were delivered to us
there are multiple man pages with the same name but that contain different
information.  Again an example of the is asa.  There are two man pages
called asa that have different information in them, one is located in 
/tools/man and the other is located in /tools/hbdcb/man.  So I have set up
a second section that will find tool man pages, it is called 'hbdcb'.
The only difference betweem hbdcb and tools is that hbdcb searches in the
reverse order of tools to find the man page you want.  They both search
all of the /tools man directories but hbdcb does it in the backward order.
the commands 'rman tools,trantor' and 'rman hbdcb,trantor' will find the
exact same man page since there is only one man page for trantor.  But for
asa which has two man pages the commands 'rman tools,asa' and 'rman hbdcb,asa'
will give you different man pages!!!  Keep this in mind if you cannot find
the exact man page you want.

   There still is no way of using the -k or -a options (keyword,apropos)
with hbdcb man pages. If you type 'rman -a guide' nothing will be found
even though there are plenty of guide man pages on lbm.  I'm still working
on this and I'll let you know when it's fixed.

						-wnw

From pjk@hpespjk Tue Aug 23 14:24 MDT 1988
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From: Pat Knebel <pjk@hpespjk>
Full-Name: Pat Knebel
Message-Id: <8808232020.AA23664@hpespjk.HP.COM>
Subject: Qspice bug workaround
To: lab@hpespjk
Date: Tue, 23 Aug 88 14:20:38 MDT
X-Mailer: Elm [version 2.01 (alpha-release)]
Status: RO

Dear Lab,

Many of you have noticed that your spice execute jobs fail, telling
you that the machine that picked up the job ran out of swap space.
The default spice execute queue is cb_300_0.  This is not good because
it allows your job to be picked up by a 350 w/o enough swap space.  
Also the 800s are not allowed to monitor this queue (because they do not
have all the tools yet).
Until the default is changed, and until we get CB1.17b, use the following 
work-around.

Use the -Q option of Qspice.

Qspice -Q cb_300 ......
    will allow your spice executions to be done by 800s or 350s

Qspice -Q cb_300_40
    will allow your spice executions to be done by only 350s
    (use this if the 800s are acting flaky)


Regards,
Qadmin

From rwm@hpesrwm Thu Jul 21 16:14 MDT 1988
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From: Russ Mason <rwm@hpesrwm>
Message-Id: <8807212207.AA09899@hpesrwm.HP.COM>
Subject: Library Locations
To: lab@hpesrwm
Date: Thu, 21 Jul 88 16:07:47 MDT
X-Mailer: Elm [version 1.7]
Status: RO


As Bill Weiner mentioned yesterday:

	The data path library has been consolidated and copied to 
		/net/hpesdds/users/libdp. (Contact rwm)

	The standard cell library (including bja's clds) has been consolidated 
	and copied to 
		/net/hpesctl/users/sclib. (Contact htt)

	The pla library has been moved to 
		/net/hpesrmn/users/pla.  (Contact rmn)

In addition:

	The i/o cells have been copied to 
		/net/hpesdds/users1/libio. (Contact rwm)

	A copy of the fid dip library is maintained in 
		/net/hpesmaj/chips/dip/release. (Contact rwm)

	A copy of the fid clock library is maintained in  
		/net/hpesdds/users/libclk. (Contact rwm)


These libraries have been pre-verified using the 1.17 tool set and 
have been drc'ed, cap-extracted, and bdl compared.  In addition, new
encap bdl has been generated for the standard cell library.  The cells 
should be ready for general consumption....let us know if you encounter
problems using the libraries.  






From dmk@hpesdmk Fri May 13 07:28 MDT 1988
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Date: Fri, 13 May 88 07:31:22 mdt
From: Don Kipp <dmk@hpesdmk>
Message-Id: <8805131331.AA18182@hpesdmk.HP.COM>
To: root@hpesrjh
Subject: Backup Failure
Status: RO

Today's date: Friday, May 13

Your machine failed to back itself up last night.  If this comes as a suprise 
to you and you want to find out why it failed, send me mail.  To run the backup
manually:

	1) Root thyself
	2) Type "/usr/local/backup/manual"

This has been a recording.

dmk



From dcw@hpesdcw Thu Apr 14 17:02 MDT 1988
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Date: Thu, 14 Apr 88 15:58:58 mst
From: Duncan Weir <dcw@hpesdcw>
Message-Id: <8804142258.AA24100@hpesdcw.HP.COM>
To: lab@hpesdcw
Subject: new laser printers
Status: RO


   We have three new laserjets in the lab.  They are located on Eric's desk,
   Bob Schuchard's aisle, and on Paul's desk.  To access the laser printers
   give a destination to the "lp" command.  The names of the laser printers
   are:
             
	     erdlj -- the laserjet on Eric's desk
	     plplj -- the laserjet on Paul's desk
	     rwmlj -- the laserjet in Bob's aisle
	     
   Example:
   
       lp -derdlj /usr/spool/lp/lptab
       
           This will print the "lptab" file on Eric's laserjet.
   
   It is possible specify options using "-o":
   
       lp -drwmlj -onb /etc/rc
           
	   This will print the "rc" file on Russ's laserjet without a banner
	   page.
   
   The complete list of options is:
   
LaserJet Options recognized:
 
   Default: normal print mode

   Primary Symbol Set: (Default Roman-8)
	r8 | -r8	Roman Extended Character Set
	k8 | -k8	Katakana Character Set

   Print Pitch Selection: (Default 10 cpi)
	10 | -10	pica print mode (10.00 cpi)
	12 | -12	elite expanded print mode (12.00 cpi)
	c  | -c		compressed print mode (16.36 cpi)

   Page orientation: (Default portrait)
	portrait	portrait mode orientation.
	landscape	landscape mode orientation.

   Output filtering: (Default Cooked)
	r  | raw	raw mode for plotting mode etc.
	i  | italics 	Translates backspace/underscore to italics
	n  | nroff	set up to properly print output from nroff
        pif             set up to properly print output from dpif (troff)
        pr              set up to properly print output from pr
	lnnn		set page length to nnn (only in cooked mode)

   Font Selection: (Default Portrait/Roman-8/10cpi/Courier)
	l  | lp		lp mode 66 lines by 170 chars compressed landscape.

   Paper control: (Default Single sided feed from paper cassette.)
	m  | man	set up for manual sheet feed
	d  | double	do double sided copy.
	legal		manually feed legal size paper.

   Bonsai emulation options: (Default Normal Print Mode)
        pp1	66 line by 80 column 1/page portrait
        pp2	66 line by 80 column 2/page portrait
        pp4	66 line by 80 column 4/page portrait
        esl	memo format
	fsd	memo format
        sso	memo format
        two	memo format
        tsbu	memo format
        tm2	Time Manager page environment
        slide	SLIDE generation filter
        Blp	66 line by 132 column 1/page line printer
        Blp2	66 line by 132 column 2/page line printer

   Other:
        nb		do not output banner page (to save paper)
        dvi             run the dvijet utility




	     


	The  understanding  is that a person has been assigned a general
	area which  applies to all systems in our  section.  Hence, Jeff
	Kehoe, who has been assigned  networking,  will  understand  and
	manage networking  issues for both s300 and s800 machines.  When
	a  new  machine  comes  on-line,  then  Jeff  will  set  up  the
	networking functions and processes.  When a machine's networking
	stops  working or screws up, Jeff will be the  person who debugs
	the problem.  In another example, Ed Ogle, who owns S800 updates
	and installs, will track S800 releases and announce when he will
	do  the  S800   updates.  The  other   administrators   need  to
	understand  how the  S800  update  will  impact  their  area and
	provide feedback on how they need to be involved with the update
	process.

	Please keep the list below handy  somewhere.  It should serve as
	your guide to get help with  problems.  Please keep me  informed
	if any of the  assignments  change.  Also, if you are interested
	in helping out in the future, then let your boss know.


	Windex/Starbase/X-Windows - Dave Lechtenberg

	S800 Updates and Installs - Ed Ogle

	S300 Updates and Installs - John Hoppal

	Networking - Jeff Kehoe

	Printers/Plotters/Text&Graphic formatting - Leith Johnson

	Discless/Global Disc Space/Backup/Recovery - Donna Griffiths

	Notes - Richard Alley
	
	Mail/Autoupdates (tnet, phone, stock) - Ed Ogle

	Hardware Support/Modems/UUCP - James Murphy

	Mechanical Engineering Applications - Stuart Yoshida

	Chipbuster EE Application - Tony Riccio

	Other EE Applications - Tom Spencer

	Computer Science Applications - Rose Maple

	SRM Management - Floyd Moore & James Murphy



