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From: "Ingo Cyliax" <cyliax@cs.indiana.edu>
Subject: Re: homebuilt 68030 plans
Message-ID: <1993Sep17.211135.11081@news.cs.indiana.edu>
Organization: Computer Science, Indiana University
References: <93259.135509KXN2@psuvm.psu.edu> <1993Sep17.102125.1038@news.cs.indiana.edu> <4013@bigfoot.first.gmd.de>
Date: Fri, 17 Sep 1993 21:11:29 -0500
Lines: 30

>  Are there any handbooks for this board?
Working on it. We are teaching a class on this platform this semester
and I am fine tuning the information included in the hardware manual.

>  Where is the monitor.listing? 
Coming. It's mostly in C and the VGA and Floppy drivers are a mess...

>  Where is the memory map.
Something like:
	DRAM 		= A31				80000000 -> ffffffff
	EPROM 		= !A31 * !A22 * !A21 * !A20	xx000000 -> xx0fffff
	SRAM 		= !A31 * !A22 * !A21 * A20	xx100000 -> xx1fffff
	MFP 		= !A31 * !A22 * A21 * !A20	xx200000 -> xx2fffff
	16 bit PC IO	= !A31 * A22 * !A21 * !A20	xx400000 -> xx4fffff
	16 bit PC MEM	= !A31 * A22 * !A21 * A20	xx500000 -> xx5fffff
	8 bit PC IO	= !A31 * A22 * A21 * !A20	xx600000 -> xx6fffff
	8 bit PC MEM	= !A31 * A22 * A21 * A20	xx700000 -> xx7fffff

>  How do you manage the refresh for the DRAM?
CAS before RAS refresh. No need for refresh counters, since they are
on the RAM. When it is time for a refresh a latch prevents the CPU from
doing a memory cycle (in case of collision) and a sequencer does a CAS
before RAS refresh cycle. 

>  Is it possible to get PCBs.
We could run another batch of boards if there is enough demand (20+boards).
 
See ya, -ingo
-- 
/* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */
